In the era of computing with single core microprocessors most compute applications developers have relied on the advances in hardware to increase the speed of their applications under the hood; the same software simply runs faster as each new generation of processors is introduced. However, this drive has slowed down since 2003 mainly due to power dissipation issues.

To achieve high performance with low power for a variety of tasks, multiprocessor SoCs and chip multiprocessors have emerged as an important class of VLSI system since its first debut a decade ago, and become more wide spread. For example, Sony PlayStation III is equipped with an 8-core IBM CELL Broadband Engine processor, Nvidia GeForce 9800 GX2 has 256 stream processors, SUN UltraSPARC T1/T2 processors have 8 cores.

Further virtually all microprocessors vendors have switched to models where multiple processing units called “processor cores” are used in each chip to increase the processing power. AMD Phenom™ X4 9000 Series Quad-Core with HyperTransport™ Technology have 4 cores, and even some of the latest Mobile workstations come with 4-core Intel® Core™ 2 i7. We expect to see anexplosion of multi processing units in the future.

However, sequential algorithms that most developers are familiar with are illplaced to take the advantage of these many-cores and multi-core systems. Rather properly parallelized algorithms and programs will be able to enjoy performance improvement with each new generation of many-cores and multicores, where multiple threads of execution cooperate to complete faster.

Unfortunately the best sequential algorithm is not necessarily the best parallel algorithm. Therefore, this tutorial will discuss the algorithm development, algorithm remapping and programming skills to enable the user harness the tremendous power of massively parallel GPUs to do general purpose computing at 1000s of GFLOPS.

This tutorial is primarily designed to serve the needs of those who require to do high performance computing for their multimedia applications where tremendous amounts of data being processed. Examples are video and audio coding and manipulation, radar signal processing, IC CAD tools, structural engineering, computational physics, molecular dynamics simulation, 3D imaging and visualization, consumer game physics, genetics, cryptography, machine intelligence, support vector machine and virtual reality products.

He was the co-author of the best paper awards for Mid West Conference in Circuits and Systems 2007, and VLSI Design Conference 1997. Saeid Nooshabadi received the MTech and PhD degrees in electrical engineering from the India Institute of Technology, Delhi, India, in 1986 and 1992, respectively.

Nathaniel Hager III received his Ph.D. in physics from State University of New York at Binghamton in 1981. He worked 12 years in R&D at Armstrong World Industries in Lancaster, developing a program on dielectric relaxation of materials as a process monitor and probe of molecular dynamics. He then worked 10 years with the Small Business Innovation Research (SBIR) program, receiving Phase I/II awards from the US Army on aerospace composite cure monitoring and Phase I awards from Department of Commerce and National Science Foundation on concrete hydration monitoring and composite structural-health monitoring. Dr. Hager’s main interest is Time Domain Reflectometry (TDR) Dielectric Spectroscopy for process monitoring applications, and he currently has a grant from NSF on concrete hydration monitoring. Dr. Hager consults for a variety of companies in the wireless, medical, aerospace, and construction industries on problems involving TDR and microwave cavity characterization.

Learn about the techniques and tools to analyze the complete serial data link including all interactions between the different elements. We will cover customized application-specific measurements that include advanced Jitter Analysis and Link Analysis with equalization. We will also discuss additional concepts needed to prepare and succeed with next-generation technologies.

Frank was born and raised in Bethlehem PA and developed an interest in Electrical / Electronic designs as a child and during High School began studies in Electrical / Electronic basics. After graduating from High School he continued an Electrical, Electronic and Computer Science education at Lehigh University, Northampton Community College and Lincoln Technical Institute. Along with over 28 additional courses across the US in microprocessor design, DC power supply designs, Audio / Video designs and Data Network and telecommunication designs.