Program for 2022 IEEE 35th International System-on-Chip Conference (SOCC)

Time Britannic Suite Main Hall The Bridge

Monday, September 5

08:00-09:00 Conference Registration & Arrival Refreshment
09:00-09:15   Opening Remarks  
09:15-10:15   Keynote I: The 21st Century Computing  
10:15-10:35 Coffee Break
10:35-11:35   Keynote II: The Evolution of the IP Industry  
11:35-12:35   Keynote III: From Adaptive Computing towards Pervasive AI  
12:35-14:05 Lunch
14:05-15:25 Industrial Session: RISC-V: Evolution, Innovation and Research Challenges of Open-ISA   Industrial Session: Silicon Photonics, a key technology for future of SOCs
15:25-15:45 Coffee Break
15:45-16:15   Invited Talk: Scaling is Failing: What Next for SoC Design  
16:15-17:45   Panel Discussion: The Impact of AI/ ML Computing on Computing Architecture and Semiconductor Technologies  
18:00-20:00   Welcome Recption  

Tuesday, September 6

08:00-09:00 Conference Registration & Arrival Refreshment
09:00-10:00   Keynote IV: Security: The Second Wave of Convergence  
10:00-11:20 Industrial Session: Emerging DPU Technologies   Industrial Session: Bringing Ray Tracing to Mobile
11:20-11:40 Coffee Break
11:40-13:00 Industrial Session: Automotive System-on-Chip Evolution and Challenges   Industrial Session: IoT Devices and Infrastructure
13:00-14:00 Lunch
14:00-15:00   Main Conference Keynote V: From ARMs to Brains  
15:00-15:20 Coffee Break
15:20-17:00 Industrial Session: Advances in Emerging SoC Technologies   Technical Session: Design for Secure and Reliable Systems
19:00-23:00 Drink Reception and Banquet Dinner

Wednesday, September 7

09:00-10:00 Conference Registration & Arrival Refreshment
10:00-11:00   Main Conference Keynote VI: Machine Learning and Hardware Security  
11:00-11:20 Coffee Break
11:20-13:00 Technical Session: Devices and Platforms for Accelerated AI/ML Computing - I   Technical Session: Circuits and Systems
13:00-13:30   Main Conference Invited Talk: EPI - European Processor Initiative - An overview on creating a European ecosystem for high performance computing  
13:30-14:30 Lunch
14:30-16:10 Technical Session: Devices and Platforms for Accelerated AI/ML Computing - II   Technical Session: Intelligent Sensing Technologies
16:10-16:30 Coffee Break
16:30-17:30   Main Conference Keynote VII: A Decade of Machine Learning Accelerators: Lessons Learned and Carbon Footprint  
17:30-18:10   Poster Introduction  
18:10-20:00   Networking Reception & Poster Session  

Thursday, September 8

08:00-09:00 Conference Registration & Arrival Refreshment
09:00-11:05 Special Session: Non-deterministic Computing Technologies Special Session: XANDAR X-by-Construction Architecture for Safety Critical Systems Special Session: Emerging Technologies for Hardware Security
11:05-11:25 Coffee Break
11:25-13:05 Technical Session: Devices and Platforms for Accelerated AI/ML Computing - III   Technical Session: Emerging and Disruptive Technologies
13:05-13:25   Closing Remarks  
13:30-14:30 Lunch

Monday, September 5

Monday, September 5 8:00 - 9:00 (Europe/London)

Conference Registration & Arrival Refreshment

Rooms: Britannic Suite, Main Hall, The Bridge

Monday, September 5 9:00 - 9:15 (Europe/London)

Opening Remarks

Sakir Sezer, NVIDIA Corporation
Room: Main Hall

Monday, September 5 9:15 - 10:15 (Europe/London)

Keynote I: The 21st Century Computing

Professor Michael Kagan, Chief Technology Officer (CTO) NVIDIA Corporation
Room: Main Hall
Chair: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))

From diseases to climate change, AI is helping us solve the worlds complex challenges. but at the same time, high volume complexity growth becomes the new standard for AI models, and it brings an ongoing need for innovative solutions to handle the intense computing demand - both in data centers, at the edge and through the clouds.

With Moore's Law coming to an end, new approaches such as parallel computing and combining multiple types of accelerated computing takes the stage. And this is exactly where NVIDIA comes in, driving innovation in multiple dimensions in both hardware and software to keep up with the demands of AI. Listen to NVIDIA CTO Michael Kagan talk about Innovation in GPUs, DPUs, CPUs, intra-server interconnect, and networking paired with new data-center architectures and new types of distributed computing. Michael's keynote will also cover new AI frameworks with more efficient algorithms and AI-optimized software to allow data center performance to run up to 1 million times faster to keep up with AI model complexity.

Monday, September 5 10:15 - 10:35 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Monday, September 5 10:35 - 11:35 (Europe/London)

Keynote II: The Evolution of the IP Industry

David Harold, Chief Marketing Officer (CMO) Imagination Technologies
Room: Main Hall
Chair: Marc Canel (IEEE & Imagination Technologies Group Ltd., USA)

In this keynote Mr. Harold will discuss the emergence of the Semiconductor IP business in the 90s spanning multiple technologies, including CPUs, GPUs, Modems and Interconnect Ips and the decisive role of various companies within the Semiconductor IP ecosystem including Imagination, Arm, Synopsys, Qualcomm, etc.

Among others the keynote will explore: The forces at play as the IP business takes off with the need for optimization of resources in value chains, The challenges of the IP business as we know it: the end of Moore's law, The emergence of data-based computing with AI/ML and how it augments traditional algorithmic computing, The emergence of new opportunities in AI/ML and system design for heterogeneous computing, The pandemic, the tensions East-West and the impact on value chains, The emergence of the hyperscalers as IP developers, Impact on key consumer and business segments, Upcoming trends and challenges, new design strategies and the emergence of the chiplet business, And the role that Imagination plays in the redefinition of the IP business.

Monday, September 5 11:35 - 12:35 (Europe/London)

Keynote III: From Adaptive Computing towards Pervasive AI

Maximilian Odendahl, Senior Director AMD
Room: Main Hall

This industrial keynote will give an introduction into Adaptive Computing and how it is uniquely positioned to tackle the computing needs powering the lives of billions. It will give an overview of the Versal Adaptive Compute Acceleration Platform, a highly integrated, multicore compute platform that can adapt with evolving and diverse algorithms. Architected around a programmable network on chip (NoC), ACAPs are easily programmed by software developers and hardware programmers alike to fit a wide range of applications and workloads.It will further present how the Xilinx Adaptive Architecture IP broadens the AMD AI product portfolio across cloud, edge and endpoint applications. An overview of the AI hardware and software strategy will be given and it will sketch how both a cooperate software unification effort across all products and new tooling initiatives will increase hardware accessibility and developer productivity

Monday, September 5 12:35 - 14:05 (Europe/London)

Lunch

Rooms: Britannic Suite, Main Hall, The Bridge

Monday, September 5 14:05 - 15:25 (Europe/London)

Industrial Session: RISC-V: Evolution, Innovation and Research Challenges of Open-ISA

Room: Britannic Suite

Abstract

Standards are known to slow down research and innovation in their area. Therefore, one might fear that the RISC-V ISA, as a standard, slows down processor and ISA development.

Interestingly though, the opposite can be observed. Pushed by politicians worldwide, many research programs around RISC-V have been defined and undertaken, and more are in preparation. Further, Universities make faster progress since they can focus on dedicated research aspects since RISC-V infrastructure and high-quality reference implementations are freely available in open source. Also freely available applications and reference implementations help to validate and compare research results with existing solutions.

In this session, leading researchers and engineers from universities and industry report on their recent research and development results around RISC-V, their challenges in bringing RISC-V to life, and how RISC-V fosters their work.

Talks

  1. "Monte Cimone: An Open RISC-V Cluster as a Research Platform for the Codesign of future RISC-V-based High Performance Computers" by Andrea Bartolini, Emanuele Parisi, Federico Ficarelli, Francesco Beneventi, Francesco Barchi, Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda, Daniele Cesarini, Andrea Acquaviva, and Luca Benini from Universita' di Bologna, E4 Engineering, CINECA, ETHZ

  2. "Focus: RISC-V in Innovation - How to bring research to application" by Ari Kulmala, Timo Hämäläinen from SoC Hub Team at Tampere University, Finland

  3. "An Industrial Perspective on RISC-V Innovation" by Keerthikumara Devarajegowda, Sebastian Prebeck, Endri Kaja, Nicolas Gerlin, Sven Wenzeck, Daniela Sanchez Lopera, Wolfgang Ecker from Infineon Technologies

14:05 Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers
Andrea Bartolini (Università di Bologna, Italy); Federico Ficarelli (CINECA SCAI, Italy); Emanuele Parisi and Francesco Beneventi (University of Bologna, Italy); Francesco Barchi (Università di Bologna, Italy); Daniele Gregori, Fabrizio Magugliani, Marco Cicala, Cosimo Gianfreda and Daniele Cesarini (E4 Computer Engineering, Italy); Andrea Acquaviva and Luca Benini (University of Bologna, Italy)

Industrial Session: Silicon Photonics, a key technology for future of SOCs

Twan Korthorst (Synopsys Inc), Pavan Bhargava (Ayar Labs), José Capmany (iPronics Programmable Photonics)
Room: The Bridge
Chair: Twan Korthorst (Synopsys, The Netherlands)

Abstract

In this special industrial session you will learn all about the history of silicon photonics technology and devices, current use in pluggable optical transceivers and the roadmap towards optical I/O for multi-die systems, programmable photonics, and optical accelerators for AI/ML. Basics of light, optics and integrated photonics will be discussed and several speakers will present a deep dive into state-of-the-art usage of silicon photonics in industry.

Talks

  1. "Introducing Silicon Photonics Technology and Design Tools" by Twan Korthorst from Synopsys Inc, Netherlands

  2. "Optical I/O for Multi-Tbps Applications" by Pavan Bhargava from Ayar Labs, USA

  3. "Programmable Silicon Photonics" by José Capmany from iPronics Programmable Photonics, Spain

Monday, September 5 15:25 - 15:45 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Monday, September 5 15:45 - 16:15 (Europe/London)

Invited Talk: Scaling is Failing: What Next for SoC Design

Zdenek Prikryl, Chief Technology Officer (CTO), Codasip
Room: Main Hall
Chair: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))

After 50 years of driving semiconductor economics, the underlying "semiconductor laws" are failing at a time when advanced manufacturing is becoming prohibitively expensive. The only viable short-term option is to match hardware to computational workload through heterogeneous computing. RISC-V's modularity combined with design automation provides a foundation for creating novel processors and domain-specific accelerators. In this talk, Codasip CTO Zdenek Prikryl will highlight the opportunities available to companies of all sizes, in seeking to differentiate and specialize their processor designs.

Monday, September 5 16:15 - 17:45 (Europe/London)

Panel Discussion: The Impact of AI/ ML Computing on Computing Architecture and Semiconductor Technologies

Rehan Ahmed (Qualcomm), James Imber Imagination Technologies), Nir Sucher (NVIDIA Corporation), Mike Hutton (Google), Michael Langan (Intel)
Room: Main Hall

Monday, September 5 18:00 - 20:00 (Europe/London)

Welcome Recption

Room: Main Hall

Tuesday, September 6

Tuesday, September 6 8:00 - 9:00 (Europe/London)

Conference Registration & Arrival Refreshment

Rooms: Britannic Suite, Main Hall, The Bridge

Tuesday, September 6 9:00 - 10:00 (Europe/London)

Keynote IV: Security: The Second Wave of Convergence

Daniel O'Loughlin, Qualcomm Technologies
Room: Main Hall
Chair: Aaron Hogan (Qualcomm, Ireland)

During the 1990's the introduction of the internet, web browser, email and resulting electronic services led to an initial commercialization wave of crypto and security technologies. During this time security technology evolved from serving the needs of government and military to solving problems in the public domain. This disruptive convergence led to new security innovations and wide adoption of security technologies in the public domain.

With the emergence of 5G, and the age of hyper-connectivity, a second wave of disruptive convergence is upon us. That second wave is defined by the hyper-connectivity of devices resulting in the adoption of these devices into high value services and deeply embedded into mission critical applications. The consequence from hyper-connectivity with respect to security risk and liability is having significant impact on the SoC industry.

In addition, today's geo-political landscape is driving regional regulatory requirements that are serving to drive global fragmentation and challenge security interoperability and scale needed to protect consumers. Today we will discuss the impact these forces are having on the future direction of SoC security technology.

Tuesday, September 6 10:00 - 11:20 (Europe/London)

Industrial Session: Bringing Ray Tracing to Mobile

Room: The Bridge
Chair: Marc Canel (IEEE & Imagination Technologies Group Ltd., USA)

Abstract

Ray Tracing is the next step in graphics technology. Ray tracing describes a method for producing visual images constructed in 3D computer graphics environments, with more photorealism than other rendering technologies. It works by tracing a path from an imaginary eye through each pixel in a virtual screen, following a ray of light and calculating the color of the object visible through it. Imagination is a pioneer and a leading developer of Ray Tracing. This presentation will describe the technology and how it is introduced in the mobile industry.

Talks

  1. "Bringing Ray Tracing to Mobile" by Kristor Beets from Imagination Technologies, UK
10:00 Machine Learning Based Parameter Tuning for Performance and Power Optimization of Multisource Clock Tree Synthesis
Prasenjit Ray, V Sai Prashant and Bindu P Rao (Intel Corporation, India)

Industrial Session: Emerging DPU Technologies

Room: Britannic Suite
Chair: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))

Abstract

Data Processing Unit (DPU) is an emerging technology targeting next generation could/enterprise datacentre server technologies, optimised for datacentre infrastructure related workloads, such as networking, virtualisation, orchestration, and security. In this special session we will have presentations given by Nvidia and Marvell, introducing their lattes DPU technology, discuss underpinning DPU architectures, DPU programming paradigms and performance centric use-case.

Talks

  1. "NVIDIA Bluefield DPU Architecture" by Idan Burstein from NVIDIA Corporation, UK

  2. "DOCA - Programming the Data Path" by John Hurley from NVIDIA Corporation, UK

  3. "Marvell DPU Architecture" by Manoj Roge from Marvell Technology Inc., USA

Tuesday, September 6 11:20 - 11:40 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Tuesday, September 6 11:40 - 13:00 (Europe/London)

Industrial Session: Automotive System-on-Chip Evolution and Challenges

Klaus Knobloch (Infineon Technologies Dresden), Alexander Frickenstein (BMW Group)
Room: Britannic Suite
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

Abstract

Driven by mobility and internet-of-things, edge-AI has become increasingly important. Whether it is home applications, autonomous driving or fields like sensor networks and drones, all benefit from local AI data processing close to the device or sensor.

Beside reducing energy consumption by avoiding high-bandwidth data transport, autonomous driving or drones doesn't even allow communication with bigger processing infrastructure due to real-time latency requirements. Processing data local at the sensor is also a key requirement to abstract such functions as services to software applications making zone controller concepts possible in automotive vehicles.

Today's AI algorithms require intensive data processing limiting the scope of edge-AI applications. Although impressive progress has been reached by technology scaling to run GPU, NPU hardware accelerators also on mobile devices, the power consumption still remains a problem to be solved. For level 5 autonomous robotaxis the overall data processing would consume appr. 30% of the battery range of today's electric cars.

Even such AI is still focused on "static" classification of data as camera images. In contrast, AI processing of time-series sensor data provides further challenges. Radar as well as systems depending on complex chemical and physical properties, such as batteries or car electric drives, need to include history in the control & prediction loop.

Recurrent neural networks (RNN) or long-short term memory (LSTM) neural networks are applied but sometimes have disadvantages in multiply and accumulate acceleration due to complex neuron structure of input, forget and output gates as well as limited data re-use. Neuromorphic spiking neural networks (SNN) are much more hardware friendly working in the digital domain, but still lack good supervised learning. New concepts are available like surrogate gradients to allow for backpropagation training.

For a radar gesture recognition, such training can be done with backpropagation through time. Efficient and small networks with only 10 hidden leaky integrate-and-fire neurons are on-par or even able to outperform LSTM networks. The network is also implemented on a digital simulation SpiNNaker2 FPGA prototype in a real time closed loop system using non-interrupt receiving to keep the local-asynchronous, global-synchronous concept. Impact of quantization and buffer memory usage is investigated to optimize accuracy, power and latency. Several approaches on spike encoding and neuron function are investigated for the gesture recognition, trading spike rate vs. accuracy. For some layers, such as the input layers for bitmaps, it is even beneficial to stay with CNN layers, resulting in a hybrid CNN-SNN model still trained end-to-end.

Implementation of such SNN concepts on established parallel processing approaches, but keeping the advantages of sparse processing, is further explored. This is done on a 3rd generation Infineon Aurix automotive μC with a parallel processing unit (PPU) for AI acceleration. By using advanced SNN training algorithms and computation cheap implementations of neuron state updates in vector operations, an alternative in comparison to LSTM networks is demonstrated with the potential of lower power consumption and faster inference times for certain applications. This shows, that advanced SNN concepts might be close to be implemented already, even in automotive products.

Talks

  1. "EVENTually driving on the Edge: Efficient Neuromorphic Concepts for Automotive Applications" by Klaus Knobloch, Pascal Gerhards, Jiaxin Huang, Felix Kreutz, Daniel Scholz from Infineon Technologies Dresden GmbH & Co. KG

  2. "Custom SoC Design for AI - The Path from Research to Industrial Application in the Automobile" by Alexander Frickenstein from BWM, Germany

  3. "Chip 4.0" by Magdy Bayoumi from University of Louisiana at Lafayette, USA

Industrial Session: IoT Devices and Infrastructure

Room: The Bridge
Chair: Rob Dimond (Arm, United Kingdom (Great Britain))

Abstract This special session is focussed on devices and infrastructure for the Internet of Things. Arm estimates that 30B connected devices are deployed today and that number is growing rapidly. Deployment of the IoT gives rise to significant challenges in low power SoC design and software deployment. In addition, these devices are supported by a global wireless infrastructure that is driving innovation in silicon.

In this session you will hear from senior technical leaders at Ericsson, Nordic Semiconductor and Arm on the challenges of the IoT & the supporting infrastructure and how they are being addressed.

Talks

  1. "Low Power Cache Design for IoT Microcontrollers" by Frode M. Pedersen from Nordic Semiconductor ASA, Norway

  2. "Ericsson Silicon" by Per-Erik Mockelind from Ericsson AB Group Function Technology, Sweden

  3. "30B+ Connected Devices, How to Scale an Ecosystem" by Robert Dimond from ARM Holdings, UK

Tuesday, September 6 13:00 - 14:00 (Europe/London)

Lunch

Rooms: Britannic Suite, Main Hall, The Bridge

Tuesday, September 6 14:00 - 15:00 (Europe/London)

Main Conference Keynote V: From ARMs to Brains

Steve Furber, University of Manchester
Room: Main Hall
Chair: John V McCanny (CBE FRS FREng IEEE Fellow FIAE, United Kingdom (Great Britain))

Starting from humble origins in the early 1980s at Acorn Computers, a small UK home company, the ARM (then ‘Acorn RISC Machine') microprocessor has gone on to dominate mobile computing and features in a wide range of other applications from the world's fastest supercomputer to datacentres to edge AI applications. One such application is SpiNNaker, the world's largest neuromorphic computing platform, that was built to accelerate understanding of the brain and thereby bring new brain-inspired concepts to AI.

Tuesday, September 6 15:00 - 15:20 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Tuesday, September 6 15:20 - 17:00 (Europe/London)

Industrial Session: Advances in Emerging SoC Technologies

Room: Britannic Suite
Chair: Norbert Schuhmann (Fraunhofer IIS, Germany)
15:20 Thermal Side-Channel Leakage Protection in Monolithic Three Dimensional Integrated Circuits
Jaya Dofe (California State University Fullerton, USA)
15:40 "High Five": Arm's First 5nm Silicon in Flip-Chip!
Pragya Laad (Arm Embedded Technologies P L, India)
16:00 Data-Centric Machine Learning Pipeline for Hardware Verification
Hongsup Shin (Arm, USA)
16:20 The Case for SoC in Future Radio Astronomy
Omar Yeste Ojeda, Nolan Denman and Stephen Wunduke (National Radio Astronomy Observatory, USA)
16:40 Divided by Designs, United by Flow- Uniquified, Modular and Automated Approach to Improve Design Efficiency
Pragya Laad and Olivier Rizzo (Arm Embedded Technologies P L, India)

Technical Session: Design for Secure and Reliable Systems

Room: The Bridge
Chair: Andrew Marshall (University of Texas at Dallas, USA)
15:20 Towards More Secure PUF Applications: A Low-Area Polar Decoder Implementation
Claus Kestel (University of Kaiserslautern, Germany); Christoph Frisch (Technical University of Munich, Germany); Michael Pehl (Technische Universität München, Germany); Norbert Wehn (University of Kaiserslautern, Germany)
15:45 A New Perspective of Inscribing Temporal Encryption on Spatial MPV Imprints for PUF Design
Xiangye Wei and Liming Xiu (BOE Technology Group, Inc, China)
16:10 RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT
Xiangdong Wei (Shanghai Jiao Tong University, China); Mohamed El-Hadedy (California State Polytechnic University Pomona, USA & University of Illinois at Urbana-Champaign, USA); Sergiu Mosanu (University of Virginia, USA); Zhengping Zhu (Shanghai Jiao Tong University, China); Wen-Mei Hwu (University of Illinois at Urbana-Champaign, USA); Xinfei Guo (Shanghai Jiao Tong University, China)
16:35 A Practical Man-In-The-Middle Attack on Deep Learning Edge Device by Sparse Light Strip Injection into Camera Data Lane
Wenye Liu, Weiyang He, Bowen Hu and Chip-Hong Chang (Nanyang Technological University, Singapore)

Tuesday, September 6 19:00 - 23:00 (Europe/London)

Drink Reception and Banquet Dinner

Dinner Speech (virtual)
Professor Lynn Conway, Emerita, University of Michigan
Rooms: Britannic Suite, Main Hall, The Bridge
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

When we imagine doing adventurous engineering out into new territory, it's fun to mentally-reenact the journeys of earlier explorers - to learn what they did and how they did it - and pattern on them. Think how the rapid spread and use of moveable-type printing in the mid-1400s escalated the Renaissance, how the daring coordinated use of compass, astrolabe and seaworthy ships in the 1500s triggered the age of exploration, and how the co-evolution of the railroads and telegraphy in the mid 1800's exponentiated the industrial revolution. Think of all the human roles and experiences during those bursts of "techno-social evolution", and of the adventures of early surfers of such big waves. By doing so, we can get "outside the bubble" and envision our own embedded, entangled roles in such waves of change. Centuries from now, archaeologists will unearth massive world-wide evidence of an era when humans designed and printed ever-more-powerful electronic machinery onto tiny chips of Silicon and used them to intelligently animate a vast landscape of innovative techno-social systems. As they ponder the tracks our clans left behind, they'll try to imagine how we all did what we did. Meanwhile, we get to live the grand adventure of surfing a "really big one"!

Wednesday, September 7

Wednesday, September 7 9:00 - 10:00 (Europe/London)

Conference Registration & Arrival Refreshment

Rooms: Britannic Suite, Main Hall, The Bridge

Wednesday, September 7 10:00 - 11:00 (Europe/London)

Main Conference Keynote VI: Machine Learning and Hardware Security

Professor Maire O'Neill, Regius Professor, Queen's University Belfast
Room: Main Hall
Chair: John V McCanny (CBE FRS FREng IEEE Fellow FIAE, United Kingdom (Great Britain))

With the globalisation of supply chains the design and manufacture of today's electronic devices are now distributed worldwide, for example, through the use of overseas foundries, third party intellectual property (IP) and third party test facilities. Many different untrusted entities may be involved in the design and assembly phases and therefore, it is becoming increasingly difficult to ensure the integrity and authenticity of devices. The supply chain is now considered to be susceptible to a range of hardware-based threats, including hardware Trojans, IP piracy, reverse engineering, IC cloning and side-channel attacks. These attacks are major security threats to military, medical, government, transportation, and other critical and embedded systems applications. This talk will explore the role machine learning has to play in hardware-based threats and in improving hardware security.

Wednesday, September 7 11:00 - 11:20 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Wednesday, September 7 11:20 - 13:00 (Europe/London)

Technical Session: Circuits and Systems

Room: The Bridge
Chair: Andrew Marshall (University of Texas at Dallas, USA)
11:20 Investigating SAMV Regarding Its Suitability for FPGAs
Farehe Giahi and Sebastian Rachuj (Friedrich-Alexander-Universität Erlangen-Nürnberg, Germany); Dietmar Fey (Chair for Computer Architecture, FAU, Erlangen, Germany)
11:45 Noise Analysis of CMOS Ring Oscillator-Based Capacitance Measurement for Lab-On-Chip Application
Javed S Gaggatur (King Consultants Education, India)
12:10 A Mixed-Signal Interface Circuit for Integration of Embedded 1T1R RRAM Arrays
Stefan Pechmann and Amelie Hagelauer (Technical University of Munich, Germany)
12:35 Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA
Yunhao Ma, Xiwei Fang, Pingcheng Dong, Xinyu Guan, Ke Li, Lei Chen and Fengwei An (Southern University of Science and Technology, China)

Technical Session: Devices and Platforms for Accelerated AI/ML Computing - I

Room: Britannic Suite
Chair: Tanja Harbaum (Karlsruhe Institute of Technology, Germany)
11:20 An Architecture for On-Chip Face Recognition in a Compressive Image Sensor
Amir Khan (Universidad de Sevilla & Consejo Superior de Investigaciones Cientifica, Spain); Jorge Fernandez-Berni and Ricardo Carmona-Galan (Institute of Microelectronics of Seville, Spain)
11:45 kNN-MSDF: A Hardware Accelerator for k-Nearest Neighbors Using Most Significant Digit First Computation
Saeid Gorgin, Mohammad Hossein Gholamrezaei, Danial Javaheri and Jeong-A Lee (Chosun University, Korea (South))
12:10 Memristive Neural Network with Efficient In-Situ Supervised Training
Santlal Prajapati (Indian Statistical Institute, India); Manobendra Nath Mondal (Indian Statistical Institute, Kolkata, India); Susmita Sur-Kolay (ISI Kolkata, India)
12:35 Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators
Taha Soliman (Bosch GmbH & University of Kaiserslautern, Germany); Amro Eldebiky (Technische Universität München, Germany); Cecilia De La Parra (Robert Bosch GmbH, Germany); Andre Guntoro (Bosch GmbH, Germany); Norbert Wehn (University of Kaiserslautern, Germany)

Wednesday, September 7 13:00 - 13:30 (Europe/London)

Main Conference Invited Talk: EPI - European Processor Initiative - An overview on creating a European ecosystem for high performance computing

Dr. Norbert Schuhmann (Fraunhofer IIS, Germany)
Room: Main Hall
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

EPI - The European Processor Initiative is a initiative currently implemented under the second stage of the EU Framework Partnership Agreement, whose aim is to design and implement a roadmap and ecosystem for a new family of low-power European processors for extreme scale computing, high-performance Big-Data and a range of emerging applications. The second implementation phase of the EPI started 1st January 2022 will continue the initial developments of Phase 1 on European microprocessors and accelerators to support European technological autonomy and sovereignty in this critical area. Based on a solid, long-term economic approach and experience, EPI will deliver central components of future European supercomputers to tackle societal challenges and boost innovation and the digital transformation of the European economy and science. The specific focus of the second phase is to finalize the development of the first generation of low-power accelerator chiplets and microprocessor units, enhancing existing technologies to target the incoming European Exascale machines, develop the second generation of and ensuring paths for industrialization and commercialization of these technologies. EPI gathers 30 renowned partners from 10 European countries to develop the processor and accelerators and ensure that the key competence of high-end chip design remains in Europe. European scientists and industry will be able to access exceptional levels of energy-efficient computing performance. This presentation gives an overview about the current activities.

Wednesday, September 7 13:30 - 14:30 (Europe/London)

Lunch

Rooms: Britannic Suite, Main Hall, The Bridge

Wednesday, September 7 14:30 - 16:10 (Europe/London)

Technical Session: Devices and Platforms for Accelerated AI/ML Computing - II

Room: Britannic Suite
14:30 Low Complexity Reconfigurable-Scalable Architecture Design Methodology for Deep Neural Network Inference Accelerator
Anagha Nimbekar, Chandrasekhara Srinivas Vatti, Dinesh Yarramsetty, Tarun Gupta, Sunidhi Singh, Ramesh Reddy Chandrapu and Amit Acharyya (IIT HYDERABAD, India)
14:55 Enhancing Adversarial Attacks on Single-Layer NVM Crossbar-Based Neural Networks with Power Consumption Information
Cory Merkel (Rochester Institute of Technology, USA)
15:20 Efficient Low-Bit-Width Activation Function Implementations for Ultra Low Power SoCs
Shenghou Ma and Paul Ampadu (Virginia Tech, USA)
15:45 FPGA Implementation of Addition-Based CORDIC-SNN with Izhikevich Neurons
Uchechukwu Leo Udeji (University of Massachusetts Lowell, USA); Martin Margala (University of Louisiana at Lafayette, USA)

Technical Session: Intelligent Sensing Technologies

Room: The Bridge
Chair: Tobias Dörr (Karlsruhe Institute of Technology, Germany)
14:30 Energy-Based Analog Neural Network Framework
Mohamed A. Watfa (LIRMM, Univ Montpellier, CNRS, France & University of Bremen, Germany); Alberto Garcia-Ortiz (University of Bremen, Germany); Gilles Sassatelli (CNRS, France)
14:55 Novel Pulse Detection System Using Differentiation: Optical Experimental Results
Sharath Patil (University of Massachusetts Lowell, USA); Bhanu Singh (Industry, USA); Raunak Borwankar (WPI, USA); Martin Margala (University of Louisiana at Lafayette, USA)
15:20 Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits
Jun Shiomi (Osaka University, Japan); Shogo Terada (Kyoto University, Japan); Tohru Ishihara (Nagoya University, Japan); Hidetoshi Onodera (Kyoto University, Japan)
15:45 A Scalable DC/DC Converter with Fast Load Transient Response and Security Improvement
Xingye Liu and Paul Ampadu (Virginia Tech, USA)

Wednesday, September 7 16:10 - 16:30 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Wednesday, September 7 16:30 - 17:30 (Europe/London)

Main Conference Keynote VII: A Decade of Machine Learning Accelerators: Lessons Learned and Carbon Footprint

David Patterson, Emeritus, University of California at Berkeley
Room: Main Hall

The success of deep neural networks (DNNs) from Machine Learning (ML) has inspired domain specific architectures (DSAs) for them. ML has two phases: training, which constructs accurate models, and inference, which serves those models. Google's first generation DSA offered 50x improvement over conventional architectures for inference in 2015. Google next built the first production DSA supercomputer for the much harder problem of training. Subsequent generations greatly improved performance of both phases. We start with ten lessons learned, such as DNNs grow rapidly; workloads quickly evolve with DNN advances; the bottleneck is memory, not floating-point units; and semiconductor technology advances unequally.

The rapid growth of DNNs rightfully raised concerns about their carbon footprint. The second part of the talk identifies the "4Ms" (Model, Machine, Mechanization, Map) that, if optimized, can reduce ML training energy by up to 100x and carbon emissions up to 1000x. By improving the 4Ms, ML held steady at <15% of Google's total energy use despite it consuming ~75% of its floating-point operations. Climate change is one of our most important problems, so ML papers should include emissions explicitly to foster competition on more than just model quality. External estimates have been off 100x-100,000x, so publishing emissions also ensures accurate accounting, which helps pinpoint the biggest challenges. With continuing focus on the 4Ms, we can realize the amazing potential of ML to positively impact many fields in a sustainable way.

Wednesday, September 7 17:30 - 18:10 (Europe/London)

Poster Introduction

Room: Main Hall
Chairs: Tanja Harbaum (Karlsruhe Institute of Technology, Germany), Fahad Siddiqui (NVIDIA Corporation, United Kingdom (Great Britain) & Queens University Belfast, United Kingdom (Great Britain))
17:30 Towards Hardware Trojan Resilient Design of Convolutional Neural Networks
Peiyao Sun, Basel Halak and Tomasz Kazmierski (University of Southampton, United Kingdom (Great Britain))
17:32 Cardinality Constrained Portfolio Optimization on an Ising Machine
Matthieu Parizy (Waseda University & Fujitsu LTD., Japan); Przemyslaw Sadowski (Fujitsu Ltd., United Kingdom (Great Britain)); Nozomu Togawa (Waseda University, Japan)
17:34 CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL
Ahmad Al-zoubi (Hamburg University of Technology & Center of Data and Computing in Natural Science, Germany); Gianluca Martino and Fin H Bahnsen (Hamburg University of Technology, Germany); Jun Zhu (Deutsches Elektronen-Synchrotron DESY, Germany); Holger Schlarb (Deutsches Elektronen Synchrotron, Germany); Goerschwin Fey (Hamburg University of Technology, Germany)
17:36 Accurate Estimation of the CNN Inference Cost for TinyML Devices
Thomas Garbay (Sorbonne University & LIP6, France); Khalil Hachicha (Université Pierre et Marie Curie, France); Petr Dobias (ETIS & ESIEE-IT, France); Wilfried Dron (UPMC, Université Pierre et Marie Curie - LIP6, Laboratoire d'Informatique de Paris 6 & EIT - SICS, France); Pedro Lusich and Imane Khalis (Wisebatt, France); Andrea Pinna and Bertrand Granado (Sorbonne University, France)
17:38 Modeling Attacks Resilient Multiple PUF-CPRNG Architecture Design Methodology
Dheeraj Agshare and Pabitra Das (IIT Hyderabad, India); Kiran Kumar A (Malla Reddy University, India); Srisubha Kalanadhabhatta (IIT Hyderabad, India); Amit Acharyya (IIT HYDERABAD, India)
17:40 Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors
Fabian Kempf, Julian Hoefer, Fabian Kreß, Tim Hotfilter, Tanja Harbaum and Juergen Becker (Karlsruhe Institute of Technology, Germany)
17:42 Energy-Efficient Black Hole Router Detection in Network-On-Chip
Luka Daoud (Boise State University, USA & Samsung Semiconductor Inc, USA); Nader Rafla (Boise State University, USA)
17:44 Performance Evaluation of High Bandwidth Memory for HPC Workloads
Amit Kumar Kabat (IIT Madras, India); Shubhang Pandey and Venkatesh Tiruchirai Gopalakrishnan (Indian Institute of Technology Madras, India)
17:46 Securing Microservices Against Password Guess Attacks Using Hardware Performance Counters
Sai Praveen Kadiyala and Xiaolan Li (Yeshiva University, USA); Wonjun Lee (California State University, USA); Andrew Catlin (Yeshiva University, USA)
17:48 MSIM: A Highly Parallel Near-Memory Accelerator for MinHash Sketch
Aman Sinha and Jhih-Yong Mai (National Yang Ming Chiao Tung University, Taiwan); Bo-Cheng Lai (National Chiao-Tung University, Taiwan)
17:50 Cache-Locality Based Adaptive Warp Scheduling for Neural Network Acceleration on GPGPUs
Weiming Hu (ShanghaiTech Unicersity, China); Yi Zhou (Glenfly Tech Co., Ltd., China); Ying Quan (Glenfly Tech Co, China); Roger Wang (Glenfly Tech Co., Ltd., China); Xin Lou (ShanghaiTech University, China)
17:52 I/O Constraints Optimization Using Machine Learning
C Lekshmi (INTEL India, India); Anmol Khatri, Sourav Saha, Shivangi Gupta, Raj Yadav and Rakshit Bazaz (Intel India, India)
17:54 Automated Deep Learning Platform for Accelerated Analog Circuit Design
Rahul Dutta (Principal Research Engineer, Singapore); Ashish James (A*STAR, Singapore); Raju Salahuddin (Institute Of Microelectronics, Singapore); Yong-Joon Jeon (Institute of Microelectronics, A*STAR, Singapore); Chuan Sheng Foo (Institute for Infocomm Research, Singapore); Kevin Chai Tshun Chuan (Scientist, Singapore)
17:56 A General Algorithm for Loop-Gain and TDC-Resolution Optimization in an ADPLL with a 2-Bit TDC Phase Detector
Abdelrahman G Habib and Mohamed Dessouky (Ain Shams University, Egypt)
17:58 A Duty Cycle Error Reduction with 1-Point Calibration Achieving 0.017UI in 7.2Gbps HBM3 DRAM Data Read
Javed S Gaggatur (Intel, Bangalore, India)

Wednesday, September 7 18:10 - 20:00 (Europe/London)

Networking Reception & Poster Session

Room: Main Hall

Thursday, September 8

Thursday, September 8 8:00 - 9:00 (Europe/London)

Conference Registration & Arrival Refreshment

Rooms: Britannic Suite, Main Hall, The Bridge

Thursday, September 8 9:00 - 11:05 (Europe/London)

Special Session: Emerging Technologies for Hardware Security

Room: The Bridge
Chairs: Chongyan Gu (Queen's University Belfast, United Kingdom (Great Britain)), He Li (University of Cambridge, United Kingdom (Great Britain))

Abstract

Recently, security issues in artificial intelligence (AI), Internet of Things (IoT), quantum information processing (QIP) and post-quantum cryptography (PQC) systems have received an increasing attention worldwide. Trustworthy high-performance AI, IoT, QIP and PQC hardware has a great impact on literally everywhere from our daily life to future homeland security. In order to address emerging threats and advance the field of hardware security, this special session collects the state-of-the-art research studies covering attacks, countermeasures, and security enhancement techniques, with six contributions from academic and industrial institutions in USA, UK, Singapore, China.

9:00 Quantum Key Distribution Post-Processing: A Heterogeneous Computing Perspective
He Li (University of Cambridge, UK); Adrian Wonfor, Amanda Weerasinghe, Muataz Alhussein and Yupeng Gong (University of Cambridge, United Kingdom (Great Britain)); Richard Penty (Cambridge University, United Kingdom (Great Britain))
9:25 A Novel Combined Correlation Power Analysis (CPA) Attack on Schoolbook Polynomial Multiplication in Lattice-Based Cryptosystems
Chuanchao Lu and Yijun Cui (Nanjing University of Aeronautics and Astronautics, China); Ayesha Khalid (Queens University Belfast, United Kingdom (Great Britain)); Chongyan Gu (Queen's University Belfast, United Kingdom (Great Britain)); Chenghua Wang and Weiqiang Liu (Nanjing University of Aeronautics and Astronautics, China)
9:50 In-Depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-Bit MCU
Jinteng Jiao (Tianjin University, China); He Li (University of Cambridge, United Kingdom (Great Britain)); Fengyan Zhao and Chengdong Qian (Phytium Technology Co., Ltd., China); Qiang Liu (Tianjin University, China)
10:15 Inconspicuous Data Augmentation Based Backdoor Attack on Deep Neural Networks
Chaohui Xu and Wenye Liu (Nanyang Technological University, Singapore); Yue Zheng (Nanyang Techological University, Singapore); Si Wang and Chip-Hong Chang (Nanyang Technological University, Singapore)
10:40 DPReDO: Dynamic Partial Reconfiguration Enabled Design Obfuscation for FPGA Security
Sandeep Sunkavilli, Nishanth Chennagouni and Qiaoyan Yu (University of New Hampshire, USA)

Special Session: Non-deterministic Computing Technologies

Room: Britannic Suite
Chairs: Olivia Chen (Tokyo City University, Japan), Renyuan Zhang (Nara Institute of Science and Technology, Japan)

Abstract

Approaching the end of Moore's roadmap, it is necessary to escape from conventional fashions of computing technologies. The non-deterministic computations have a potential to efficiently improve the quality of service (QoS) without benefiting by scaling-down of devices, which include but not limit to approximate-, probabilistic-, analog-, and spike-coded computing fashions. The innovation of SoCs is driven by the demands on the front- and back-ends. As stated in the SOCC's scope, the emerging "Digital Society" covers the full schemes from foundations to applications.

This special session involves the research works on quantum device, NN-acceleration architecture, medical and communication applications for demonstrating benefits and challenges of non-deterministic computing technologies.

9:00 A Stochastic Coding Method of EEG Signals for Sleep Stage Classification
Guangxian Zhu, Huijia Wang and Yirong Kan (Nara Institute of Science and Technology, Japan); Zheng Chen (Osaka University, Japan); Ming Huang, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang and Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
9:25 Non-Deterministic Quantization for mmWave Beam Prediction
Haohui Jia, Na Chen, Renyuan Zhang and Minoru Okada (Nara Institute of Science and Technology, Japan)
9:50 Application and Evaluation of Quantization for Narrow Bit-Width Resampling of Sequential Monte Carlo
Hiroki Nishimoto, Renyuan Zhang and Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
10:15 Design and Implementation of Stochastic Neural Networks Using Superconductor Quantum-Flux-Parametron Devices
Olivia Chen (Tokyo City University, Japan); Yanzhi Wang (Northeastern University, USA); Renyuan Zhang (Nara Institute of Science and Technology, Japan); Nobuyuki Yoshikawa (Yokohama National University, Japan)
10:40 GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights
Man Wu (Keio University, Japan); Yirong Kan, Renyuan Zhang and Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)

Special Session: XANDAR X-by-Construction Architecture for Safety Critical Systems

Room: Main Hall
Chair: Fahad Siddiqui (NVIDIA Corporation, United Kingdom (Great Britain) & Queens University Belfast, United Kingdom (Great Britain))

Abstract

The advancements of next generation networked embedded systems (ES) has initiated the need for software technologies that facilitate rapid prototyping and high performance while enhancing systems' resilience by establishing, maintaining trustworthiness and assuring system safety and security. However, heavy reliance on Machine Learning (ML) and Artificial Intelligence (AI) to design and develop next generation networked embedded systems system renders serious software and hardware design challenges including trust, security, reliability and operational safety. Prime examples are autonomous vehicles that are prone to various safety/security vulnerabilities that could lead to serious incidents causing physical harm and damage to the physical environment and to the general public. Approaches that reduce development costs and minimize the risk caused by hardware and software failure of such autonomous and intelligent systems deployed in safety critical environments are essential in order to maintain vital services and public confidence in them.

The scope of the XANDAR project aligns with the specific challenges of Call ID ICT-50-2020, with research and innovation in both subtopics of development tools & methods for interoperable, adaptive, secure and trustworthy software as well as advanced software systems and architectures.

Technical Presentations

09:00 Overview of XANDAR Project

Tobias Dörr from (Karlsruhe Institute of Technology, Germany)

09:25 Implementation of ML based Airborne Collision Avoidance System on FPGAs

Phillip Noeldeke from (German Space Agency)

9:00 Overhead-Aware Schedule Synthesis for Logical Execution Time (LET) in Automotive Systems
Erjola Lalo and Andreas Sailer (Vector Informatik GmbH, Germany); Christian Siemers (Clausthal University of Technology, Germany); Juergen Mottok (Ostbayerische Technische Hochschule, Germany)
9:25 Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development
Florian Schade, Tobias Dörr and Juergen Becker (Karlsruhe Institute of Technology, Germany)
9:45 Towards Automating a Software-Centered Development Process That Considers Timing Properties
Raphael Weber, Nico Adler, Thomas Wilhelm, Andreas Sailer and Clemens Reichmann (Vector Informatik GmbH, Germany)

Thursday, September 8 11:05 - 11:25 (Europe/London)

Coffee Break

Rooms: Britannic Suite, Main Hall, The Bridge

Thursday, September 8 11:25 - 13:05 (Europe/London)

Technical Session: Devices and Platforms for Accelerated AI/ML Computing - III

Room: Britannic Suite
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)
11:25 Implementation and Evaluation of Deep Neural Networks in Commercially Available Processing in Memory Hardware
Prangon C Das, Purab R Sutradhar and Mark Indovina (Rochester Institute of Technology, USA); Sai Manoj Pudukotai Dinakarrao (George Mason University, USA); Amlan Ganguly (Rochester Institute of Technology, USA)
11:50 Hardware Oriented Strip-Wise Optimization (HOSO) Framework for Efficient Deep Neural Network
Xiaotian Ma (California State University Fullerton, USA); Kevin Han (Cal State Fullerton, USA); Yucheng Yang (Ecotron Corp, USA); Ronald F DeMara (University of Central Florida, USA); Yu Bai (California State University Fullerton, USA)
12:15 RRAM-Based Neural Radiance Field Processor
Yueyang Zheng, Chaolin Rao and Haochuan Wan (ShanghaiTech University, China); Yuliang Zhou (InnoStar Semiconductor, China); Pingqiang Zhou, Jingyi Yu and Xin Lou (ShanghaiTech University, China)
12:40 An Efficient FPGA Accelerator for Point Cloud
Zilun Wang, Wendong Mao, Peixiang Yang, Zhongfeng Wang and Jun Lin (Nanjing University, China)

Technical Session: Emerging and Disruptive Technologies

Room: The Bridge
Chair: Martin Margala (University of Louisiana at Lafayette, USA)
11:25 A Versatile & Adjustable 400 Node CMOS Oscillator Based Ising Machine to Investigate and Optimize the Internal Computing Principle
Markus Graber (Technical University of Darmstadt, Germany); Klaus Hofmann (TU Darmstadt, Germany)
11:50 Virtual Platform Acceleration Through Userspace Host Execution
Lukas Juenger and Antonios Salios (RWTH Aachen University, Germany); Peter Blöcher (Audi AG, Germany); Rainer Leupers (RWTH Aachen University, Germany)
12:15 In-Network Accumulation: Extending the Role of NoC for DNN Acceleration
Binayak Tiwari (University of Nevada Las Vegas, USA); Mei Yang (University of Nevada, Las Vegas, USA); Xiaohang Wang (South China University of Technology, China); Yingtao Jiang (University of Nevada, Las Vegas, USA)

Thursday, September 8 13:05 - 13:25 (Europe/London)

Closing Remarks

Sakir Sezer, Jürgen Becker, Andrew Marshall, Thomas Buchner
Room: Main Hall

Thursday, September 8 13:30 - 14:30 (Europe/London)

Lunch

Rooms: Britannic Suite, Main Hall, The Bridge

Program last updated on Aug 9, 2022 20:16 UTC