Program for 2021 IEEE 34th International System-on-Chip Conference (SOCC)

Time Virtual Room I Virtual Room 2+3

Tuesday, September 14

05:55 am-08:15 am   TU: Tutorials

Wednesday, September 15

09:00 am-09:15 am Opening Ceremony  
09:15 am-10:15 am K1: Opening Keynote Address  
10:15 am-10:30 am Break  
10:30 am-11:30 am TS1: Deep Neural Network Acceleration via FPGAs  
11:30 am-12:30 pm TS2: Future technologies and circuits and energy harvesting  
12:30 pm-01:30 pm Lunch Break  
01:30 pm-02:30 pm TS3: Novel circuits and analysis for applications  
02:30 pm-03:30 pm DT: Design Track Session  
03:30 pm-04:30 pm PS1: Poster Session I: Circuits and Systems  
04:30 pm-05:30 pm SS2: Challenges and Opportunities in AI and Big Data Applications  

Thursday, September 16

09:00 am-10:00 am K2: Keynote II: "Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems"  
10:00 am-10:30 am Break  
10:30 am-11:30 am TS4: Novel Workload Acceleration Techniques  
11:30 am-12:30 pm TS5: Novel techniques for Security and resilience  
12:30 pm-01:30 pm Lunch Break  
01:30 pm-02:30 pm TS6: Advanced Power, Noise and Reliability Analysis  
02:30 pm-03:30 pm SS1: Special Session 1: Hardware Security  
03:30 pm-04:30 pm PS2: Poster Session II: Applications and Accelerations  
04:30 pm-05:15 pm SS3: Hardware Design for Deep Neural Networks  
05:15 pm-05:30 pm Closing Remarks  

Friday, September 17

06:50 am-09:50 am IF: Industry Forum on High Speed SoC Interconnects (virtual only)  

Tuesday, September 14

Tuesday, September 14 5:55 - 8:15

TU: Tutorials

Virtual Room 2+3

Wednesday, September 15

Wednesday, September 15 9:00 - 9:15

Opening Ceremony

Venki Muthukumar, General Chair, Gang Qu, Technical Program Chair
Virtual Room I
Chairs: Venkatesan Muthukumar (University of Nevada Las Vegas, USA), Danella Zhao (Old Dominion University, USA), Gang Qu (University of Maryland, USA)

Wednesday, September 15 9:15 - 10:15

K1: Opening Keynote Address

Human-Centric Computing
Prof. Jan Rabaey, CTO, STCO Division, IMEC, Belgium, and Professor, EECS Dept., Univ. of California at Berkeley
Virtual Room I
Chair: Danella Zhao (Old Dominion University, USA)

Wednesday, September 15 10:15 - 10:30

Break

Virtual Room I

Wednesday, September 15 10:30 - 11:30

TS1: Deep Neural Network Acceleration via FPGAs

Virtual Room I
Chair: Andrew Marshall (University of Texas at Dallas, USA)
10:30 Implementation and Evaluation of a Neural Network-Based LiDAR Histogram Processing Method on FPGA
Gongbo Chen (Fraunhofer IMS, Germany); Giray Atabey Kirtiz (University of Duisburg-Essen, Germany); Christian Wiede (Fraunhofer IMS, Germany); Rainer Kokozinski (University of Duisburg-Essen, Germany)
10:45 FPGA Implementation of a Reconfigurable Recurrent Neural Networks (RNN) Unit
Michael Wasef and Nader Rafla (Boise State University, USA)
11:00 Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA
Mahesh M (Indian Institute of Information Technology Kottayam, India); Nalesh S (CUSAT, India); Kala S (Indian Institute of Information Technology Kottayam, India)
11:15 Tufan: Low-Power Throughput Architecture for Acceleration of EfficientNet on Cloud FPGAs
Mohammadreza Baharani, Ushma Bharucha, Kaustubh Mhatre and Hamed Tabkhi (University of North Carolina at Charlotte, USA)

Wednesday, September 15 11:30 - 12:30

TS2: Future technologies and circuits and energy harvesting

Virtual Room I
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)
11:30 Optimizing Quantum Circuits for Arbitrary State Synthesis and Initialization
Naveed Mahmud, Andrew GJ MacGillivray, Manu Chaudhary and Esam El-Araby (University of Kansas, USA)
11:45 Optimization of 3D Stacked Nanosheets in 5nm Gate-All-Around Transistor Technology
Anil Gundu Kumar (The Hong Kong University of Science and Technology, Hong Kong); Volkan Kursun (UST HongKong, Hong Kong)
12:00 Dual-Band GSM Energy Harvester for Duty-Cycle Approach in 180nm CMOS Technology
Hugo Daniel Hernandez, Diego Augusto Pontes and Bruno Soares (Universidade Federal de Minas Gerais, Brazil); Dionísio Carvalho (University of São Paulo & USP, Brazil); Wilhelmus Van Noije (University of São Paulo, São Paulo, Brazil)
12:15 Stereolithography-Based Rectenna for Wireless Energy Harvesting
Xuan Viet Linh Nguyen (INSA Lyon, France); Tony Gerges (Ampere, France); Jean-Marc Duchamp (University Grenoble Alpes & G2Elab, France); Philippe Benech (Université de Grenoble-Alpes, G2ELab, France); Jacques Verdier (Institut National des Sciences Appliquées, France); Philippe Lombard (University of Lyon, France); Michel Cabrera (Université de Lyon, France); Bruno Allard (INSA Lyon, France)

Wednesday, September 15 12:30 - 1:30

Lunch Break

Virtual Room I

Wednesday, September 15 1:30 - 2:30

TS3: Novel circuits and analysis for applications

Virtual Room I
Chair: Venkatesan Muthukumar (University of Nevada Las Vegas, USA)
1:30 Software-Defined Temporal Decoupling in Virtual Platforms
Lukas Juenger, Alexander Belke and Rainer Leupers (RWTH Aachen University, Germany)
1:45 Embedded ICG-Based Stroke Volume Measurement System: Comparison of Discrete-Time and Continuous-Time Architectures
Antoine Gautier (University of Lille, Junia, France)
2:00 Analysis of the Sub-μA Fully Integrated NMOS LDO for Backscattering System
Puyang Zheng (Stony Brook University, USA); Xiao Sha (Stonybrook University, USA); Milutin Stanacevic (SUNY Stony Brook, USA)
2:15 A SiPM Based Sensor for Nuclear Detection Applications
Shahram Hatefi Hesari (The University of Tennessee, Knoxville, USA); Nicole McFarlane (University of Tennessee, USA)

Wednesday, September 15 2:30 - 3:30

DT: Design Track Session

Virtual Room I
Chair: Md Tanvir Arafin (Morgan State University, USA)
2:30 A Design Approach to Reduce Test Time on SOC Memories
Dieu Van Dinh (NXP Semiconductor, Inc., USA); Prokash Ghosh (NXP Semiconductor Inc & Indian Institute of Technology, Bombay, India); Misal Varma (NXP Semiconductor, Inc., India)
2:42 LC- Physical Unclonable Function in 3D Wireless IC for Securing the Internet of Things Devices
Jaya Dofe (California State University Fullerton, USA); Wafi Danesh (University of Missouri Kansas City, USA)
2:54 Reinforcement Learning-Based Power Management Architecture
David Akselrod (Advanced Micro Devices, Canada)
3:06 An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce Annotations
Rodrigue Rizk (The Center for Advanced Computer Studies, University of Louisiana at Lafayette, USA); Dominick Rizk, Frederic Rizk and Ashok Kumar (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Magdy Bayoumi (University of Louisiana at Lafayette, USA)
3:18 A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable Function
Dominick Rizk (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Rodrigue Rizk (The Center for Advanced Computer Studies, University of Louisiana at Lafayette, USA); Frederic Rizk and Ashok Kumar (The Center for Advanced Computer Studies University of Louisiana at Lafayette, USA); Magdy Bayoumi (University of Louisiana at Lafayette, USA)

Wednesday, September 15 3:30 - 4:30

PS1: Poster Session I: Circuits and Systems

Virtual Room I
Chair: Jinjun Xiong (IBM T. J. Watson Research Center, USA)
3:30 FLECSim-SoC: A Flexible End-To-End Co-Design Simulation Framework for System on Chips
Tim Hotfilter, Julian Hoefer, Fabian Kreß, Fabian Kempf and Juergen Becker (Karlsruhe Institute of Technology, Germany)
3:36 Generating Hardware and Software for RISC-V Cores Generated with Rocket Chip Generator
Suleyman Savas (Huawei Technologies, Switzerland); Jorn Janneck (Lund University, Sweden); Endri Bezati (EPFL SCI STI MM, Switzerland)
3:42 Implementation of an SoC Architecture with Built-In Safety Features
Tibor Gergely Markovits, György Rácz and Péter Arató (Budapest University of Technology and Economics, Hungary)
3:48 Power Swapper: Approximate Functional Block Assisted Cryptosystem Security
Abhijitt Dhavlle (George Mason University, USA); Setareh Rafatirad and Houman Homayoun (University of California Davis, USA); Sai Manoj Pudukotai Dinakarrao (George Mason University, USA)
3:54 TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCs
Aditya Kulkarni and Ayush Singh (Samsung Semiconductor India Research, India); Sachin Waje (National Institute of Technology Karnataka, Surathkal, India); Sunil Kashide (Samsung Semiconductor India Research, India); Seonil Choi (Samsung Electronics Co. Ltd., Korea (South))
4:00 Performance Optimization of p-Channel SnO Cylindrical Thin Film Transistors (CTFT) Using 3D Modelling
Viswanath G Akkili and Viranjay M. Srivastava (University of KwaZulu-Natal, South Africa)
4:06 1.81 kHz Relaxation Oscillator with Forward Bias Comparator and Leakage Current Compensation Based Techniques
Xiao Sha (Stonybrook University, USA); Puyang Zheng (Stony Brook University, USA); Milutin Stanacevic (SUNY Stony Brook, USA)
4:12 Real-Time Framework Optimized for Low Latency Quantum Computing Experiments
Richard Gebauer, Nick Karcher, Jonas Hurst and Marc Weber (Karlsruhe Institute of Technology, Germany); Oliver Sander (KIT, Germany)

Wednesday, September 15 4:30 - 5:30

SS2: Challenges and Opportunities in AI and Big Data Applications

From the Perspectives of Chip Design and Data Management
Virtual Room I
Chair: Yu-Guang Chen (National Central University, Taiwan)
4:30 Neural Network Based Branch Predictor Design for Energy Harvesting Powered Systems
Weifan Sun and Xiaojun Cai (Shandong University, China); Mengying Zhao (School of Computer Science and Technology, Shandong University, China); Zhiping Jia (Shandong University, China)
4:45 Total Variation Reduction for Lossless Compression of HPC Applications
Huizhang Luo (Hunan University, China); Junqi Wang (Rutgers University at Newark, USA); Yida Li and Kenli Li (Hunan University, China)
5:00 Can We Trust Machine Learning for Electronic Design Automation?
Kang Liu (Huazhong University of Science and Technology, China); Jun Zhang (NYU, USA); Benjamin Tan (New York University, USA); Dan Feng (Huazhong University of Science and Technology, China)
5:15 Efficient Localization of Origins of PVC Based on Random Signal Segmentation
Dawei Li and C. Liu (South-Central University for Nationalities, China); Xiaowei Xu (Guangdong General Hospital, China)

Thursday, September 16

Thursday, September 16 9:00 - 10:00

K2: Keynote II: "Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems"

Kaushik Roy, Edward G. Tiedemann Jr. Distinguished Professor, and Director C-BRIC Purdue University, West Lafayette, IN
Virtual Room I
Chair: Jinjun Xiong (IBM T. J. Watson Research Center, USA)

Thursday, September 16 10:00 - 10:30

Break

Virtual Room I

Thursday, September 16 10:30 - 11:30

TS4: Novel Workload Acceleration Techniques

Virtual Room I
Chair: Hao Cai (Southeast University, China)
10:30 On Reduction of Computations for Threshold Function Identification
Wen-Chih Hsu, Chia-Chun Lin and Yi-Ting Li (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan)
10:45 Design and Optimization of a Pruning-Efficient DCNN Inference Accelerator
Che-Hao Chang and Chih-Tsun Huang (National Tsing Hua University, Taiwan)
11:00 Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm
Pingcheng Dong, Zhuoyu Chen, Zhuoao Li, Xiwei Fang, Huanshihong Deng, Ruoheng Yao, Yunhao Ma and Wenyue Zhang (Southern University of Science and Technology, China); Lei Chen (Pengcheng Laboratory, China); Fengwei An (Southern University of Science and Technology, China)

Thursday, September 16 11:30 - 12:30

TS5: Novel techniques for Security and resilience

Virtual Room I
Chair: Basel Halak (Southampton University, United Kingdom (Great Britain))
11:30 Key-Based Obfuscation Using HT-Like Trigger Circuit for 128-Bit AES Hardware IP Core
Surbhi Chhabra and Kusum Lata (The LNM Institute of Information Technology, Jaipur, India)
11:45 Identifying Specious LUTs for Satisfiability Don't Care Trojan Detection
Lingjuan Wu (Huazhong Agricultural University, China); Xuefei Li, Jiacheng Zhu, Jian Zheng and Wei Hu (Northwestern Polytechnical University, China)
12:00 ReCPE: A PE for Reconfigurable Lightweight Cryptography
Jeff Anderson (The George Washington University, USA); Yousra Alkabani (Halmstad University, Sweden); Tarek El-Ghazawi (The George Washington University, USA)
12:15 RARES: Runtime Attack Resilient Embedded System Design Using Verified Proof-Of-Execution
Avani Dave (University of Maryland, Baltimore County, USA & UMBC, USA)

Thursday, September 16 12:30 - 1:30

Lunch Break

Virtual Room I

Thursday, September 16 1:30 - 2:30

TS6: Advanced Power, Noise and Reliability Analysis

Virtual Room I
Chair: Lei Yang (University of New Mexico, USA)
1:30 Dynamic Power Analysis of Standard-Cell FPGA Fabrics
Bo Bao and Jason Anderson (University of Toronto, Canada)
1:45 Crosstalk Noise Based Configurable Computing: A New Paradigm for Digital Electronics
Md Arif Iqbal (University of Missouri Kansas City, USA); Naveen Macha (NVIDIA Corporation, USA); Bhavana Repalle (Intel Corporation, USA); Sehtab Hossain (University of Missouri Kansas City, USA); Mostafizur Rahman (University of Missouri-Kansas City, USA)
2:00 A Framework for Evaluation of Debug Path Performance in SoC
Prokash Ghosh (NXP Semiconductor Inc & Indian Institute of Technology, Bombay, India); Khwahish Sinha (NXP Semiconductor Inc, India)
2:15 On the Stability, Transient and Quiescent Current Control of One Low-Voltage Class-AB Op-Amp Architecture
Aniruddha Roy, Khyati Bansal and Nitin Agarwal (Texas Instruments, India)

Thursday, September 16 2:30 - 3:30

SS1: Special Session 1: Hardware Security

Virtual Room I
Chairs: Md Tanvir Arafin (Morgan State University, USA), Kevin Kornegay (Morgan State University, USA)
2:30 Analog-Inspired Hardware Security: A Low-Energy Solution for IoT Trusted Communications
Samuel D Ellicott (The Ohio State University, USA); Yu Qi (Case Western Reserve University, USA); Michael Kines (The Ohio State University, USA); Abdullah Kurtoglu (Case Western Reserve University, USA); Waleed Khalil (The Ohio State University, USA); Hossein Lavasani (Case Western Reserve University, USA)
2:45 LDO-Based Odometer to Combat IC Recycling
Rabin Y Acharya and Domenic Forte (University of Florida, USA); Michael Levin (Honeywell Aerospace, USA)
3:00 Saidoyoki: Evaluating Side-Channel Leakage in Pre- and Post-Silicon Setting
Pantea Kiaei, Zhenyuan Liu and Ramazan Kaan Eren (Worcester Polytechnic Institute, USA); Yuan Yao (Virginia Tech, USA); Patrick Schaumont (Worcester Polytechnic Institute, USA)
3:15 Distributed On-Chip Power Supply for Security Enhancement in Multicore NoC
Xingye Liu and Paul Ampadu (Virginia Tech, USA)

Thursday, September 16 3:30 - 4:30

PS2: Poster Session II: Applications and Accelerations

Virtual Room I
Chair: Fakhrul Zaman Rokhani (University Putra Malaysia, Malaysia)
3:30 A Two-Stage Path Planning Engine for Robot Navigation System
Yu-En Hsu (National Yang Ming Chiao Tung University, Taiwan)
3:36 An IMU-Aided Fitness System
Yi-Ting Lin, Chun-Jui Chen and Pei-Yi Kuo (National Tsing Hua University, Taiwan); Si-Huei Lee (Taipei Veterans General Hospital, Taiwan); Chia-Chun Lin, Yun-Ju Lee and Yi-Ting Li (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan)
3:42 Cluster Tool Performance Analysis Using Graph Database
Shiuan-Hau Huang and Hsin-Ping Yen (National Tsing Hua University, Taiwan); Yan-Hsiu Liu, Kuang-Hsien Tseng and Ji-Fu Kung (United Microelectronics Corporation, Taiwan); Chia-Chun Lin and Yi-Ting Li (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan)
3:48 NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators
Melvin E. Galicia (RWTH Aachen University, Germany); Ali BanaGozar (Eindhoven University of Technology, The Netherlands); Karl J. X. Sturm and Felix Staudigl (RWTH Aachen University, Germany); Sander Stuijk (Eindhoven University of Technology, The Netherlands); Henk Corporaal (Technical University Eindhoven, The Netherlands); Rainer Leupers (RWTH Aachen University, Germany)
3:54 FPNA: A Reconfigurable Accelerator for AI Inference at the Edge
Peter Gadfort and Oluseyi Ayorinde (DEVCOM Army Research Laboratory, USA)
4:00 Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems
Nidhi Anantharajaiah (Karlsruhe Institute of Technology, Germany); Felix Knopf (Karlsruhe Institute for Technology, Germany); Juergen Becker (Karlsruhe Institute of Technology, Germany)
4:06 Design Study on Impact of Memory Access Parallelism for Cloud FPGAs
Arnab Ardhendu Purkayastha and Hamed Tabkhi (University of North Carolina at Charlotte, USA)
4:12 Combined Side-Channel Attacks on a Lightweight Prince Cipher Implementation
Soner Seckiner and Selcuk Köse (University of Rochester, USA)
4:18 GPU-Based Acceleration of Fully Parallel Annealing Algorithm for Combinatorial Optimization
Kazushi Kawamura, Kaisei Okawa, Gregory Gutmann, Thiem Chu, Jaehoon Yu and Masato Motomura (Tokyo Institute of Technology, Japan)

Thursday, September 16 4:30 - 5:15

SS3: Hardware Design for Deep Neural Networks

Virtual Room I
Chair: Yu-Guang Chen (National Central University, Taiwan)
4:30 A Convolutional Neural Network on Chip Design Methodology for CNN Hardware Implementation
Kun-Chih Chen, Yi-Sheng Liao and Cheng-Kang Tsai (National Sun Yat-Sen University, Taiwan)
4:45 Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by Faults
Jin-Fu Li and Yung-Yu Tsai (National Central University, Taiwan)
5:00 A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks
Yu-Guang Chen, Chi-Wei Hsu, Hung-Yi Chiang, Tsung-Han Hsieh and Jing-Yang Jou (National Central University, Taiwan)

Thursday, September 16 5:15 - 5:30

Closing Remarks

Virtual Room I

Friday, September 17

Friday, September 17 6:50 - 9:50

IF: Industry Forum on High Speed SoC Interconnects (virtual only)

Virtual Room I