Program for 2020 IEEE 33rd International System-on-Chip Conference (SOCC)

Time Virtual Room 1 Virtual Room 2 Virtual Room 3

Tuesday, September 8

09:00 am-10:00 am TA1: Tutorial 1 TB1: Tutorial 2  
10:00 am-10:30 am TC1: Industry Forum - Talk 1
10:30 am-10:45 am Virtual Coffee Break TC2: Industry Forum - Talk 2
10:45 am-11:00 am TA2: Tutorial 3 TB2: Tutorial 4
11:00 am-11:10 am Virtual Coffee Break
11:10 am-12:15 pm  
11:10 am-11:40 am TC3: Industry Forum - Talk3
11:40 am-12:10 pm TC4: Industry Forum - Talk4
12:10 pm-12:20 pm Virtual Coffee Break
12:20 pm-12:50 pm     TC5: Industry Forum - Panel

Wednesday, September 9

09:00 am-09:10 am WL: Welcome Address    
09:10 am-10:10 am WR1: Technical Session 1 WS1: Special Session 1  
10:10 am-10:20 am Virtual Coffee Break  
10:20 am-11:05 am WK1: Keynote1    
11:05 am-11:10 am Virtual Coffee Break  
11:10 am-11:55 am WK2: Keynote 2    
11:55 am-12:00 pm Virtual Coffee Break  
12:00 pm-01:00 pm WR2: Technical Session 2 WS2: Special Session 2 WP1: Poster Session 1

Thursday, September 10

09:00 am-10:00 am TR3: Technical Session 3 TS3: Special Session 3 TP2: Poster Session 2
10:00 am-10:10 am Virtual Coffee Break  
10:10 am-10:55 am TK3: Keynote 3    
10:55 am-11:05 am Virtual Coffee Break  
11:05 am-11:50 am TK4: Keynote 4    
11:50 am-12:00 pm Virtual Coffee Break  
12:00 pm-01:00 pm TR4: Technical Session 4 TS4: Special Session 4  

Friday, September 11

09:00 am-10:00 am FR5: Technical Session 5 FS5: Special Session 5  
10:00 am-10:10 am Virtual Coffee Break  
10:10 am-10:55 am FK5: Keynote 5    
10:55 am-11:05 am Virtual Coffee Break  
11:05 am-11:50 am FK6: Keynote 6    
11:50 am-12:00 pm Virtual Coffee Break  
12:00 pm-01:00 pm FR6: Technical Session 6 FDT: Design Track  
01:00 pm-01:10 pm FCR: Concluding Remarks    

Tuesday, September 8

Tuesday, September 8 9:00 - 10:30

TA1: Tutorial 1

ENERGY-EFFICIENT MEMORY-CENTRIC ACCELERATOR DESIGN FOR MOBILE/EDGE-BASED AI INFERENCE
PO-TSANG HUANG, NATIONAL CHIAO TUNG UNIV., TAIWAN
Virtual Room 1
Chair: Selcuk Kose (University of Rochecter, USA)

TB1: Tutorial 2

ANNEALING PROCESSING AND EMERGING NONVOLATILE MEMORY FOR AI CHIPS
TAKAYUKI KAWAHARA, TOKYO UNIV. OF SCIENCE, JAPAN
Virtual Room 2
Chair: Lan-Da Van (National Yang Ming Chiao Tung University, Taiwan)

Tuesday, September 8 10:00 - 10:30

TC1: Industry Forum - Talk 1

High-Speed Electrical I/O Interfaces and Interconnects from 56 Gbps to 112Gbps and Beyond
Dr. Peng Mike Li, Intel Fellow
Virtual Room 3
Chair: Thanh T Tran (Rice University, USA)

Tuesday, September 8 10:30 - 10:45

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Tuesday, September 8 10:30 - 11:00

TC2: Industry Forum - Talk 2

Versal-ACAP Architecture, Programming, Machine Learning and 5G
Dr. Chris Dick, Xilinx Fellow/DSP Chief Architect
Virtual Room 3
Chair: Thanh T Tran (Rice University, USA)

Tuesday, September 8 10:45 - 12:15

TA2: Tutorial 3

EFFICIENT POWER DESIGN FOR IOT/IIOT & 5G APPLICATIONS
BRIAN ZAHNSTECHER, POWERROX LLC, USA
Virtual Room 1
Chair: Selcuk Kose (University of Rochecter, USA)

TB2: Tutorial 4

PORTABLE AND SCALABLE HIGH VOLTAGE CIRCUITS FOR AUTOMOTIVE APPLICATIONS IN BICMOS PROCESSES
SRI NAVANEETH EASWARAN, TEXAS INSTRUMENTS, USA
Virtual Room 2
Chair: Lan-Da Van (National Yang Ming Chiao Tung University, Taiwan)

Tuesday, September 8 11:00 - 11:10

Virtual Coffee Break

Virtual Room 3

Tuesday, September 8 11:10 - 11:40

TC3: Industry Forum - Talk3

High-Speed Signal Integrity Challenges and Opportunities for Next Generation Technologies
Dr. Bhyrav Mutnury, Senior Distinguished Engineer and Global Team Lead, Dell EMC
Virtual Room 3
Chair: Thanh T Tran (Rice University, USA)

Tuesday, September 8 11:40 - 12:10

TC4: Industry Forum - Talk4

Challenges and Solutions for High-Bandwidth Density, Energy-Efficient, Short-Reach Signaling that Enables Massively Scalable Parallelism
Dr. John Wilson, Senior Research Scientist, Nvidia Research
Virtual Room 3
Chair: Thanh T Tran (Rice University, USA)

Tuesday, September 8 12:10 - 12:20

Virtual Coffee Break

Virtual Room 3

Tuesday, September 8 12:20 - 12:50

TC5: Industry Forum - Panel

Virtual Room 3
Chairs: Juergen Becker (Karlsruhe Institute of Technology, Germany), Thanh T Tran (Rice University, USA)

Wednesday, September 9

Wednesday, September 9 9:00 - 9:10

WL: Welcome Address

Virtual Room 1
Chair: Danella Zhao (Old Dominion University, USA)

Wednesday, September 9 9:10 - 10:10

WR1: Technical Session 1

Security
Virtual Room 1
Chairs: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain)), Md Farhadur Reza (Eastern Illinois University, USA)
9:10 HARDY: Hardware Based Analysis for malwaRe Detection in Embedded sYstems
Sai Praveen Kadiyala (Yeshiva University, USA); Mohit Garg (Birla Institute of Technology and Science (BITS) Pilani, India); Manaar Alam (IIT Kharagpur, India); Hau Ngo (United States Naval Academy, USA); Debdeep Mukhopadhyay (IIT Kharagpur, India); Srikanthan Thambipillai (Nanyang Technological University, Singapore)
9:25 A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security
Yuchen Mei, Yuan Du, Li Du and Xuewen He (Nanjing University, China); Xiaoliang Chen (University of California, Irvine, USA); Zhongfeng Wang (Nanjing University, China)
9:40 Evolution of Embedded Platform Security Technologies: Past, Present & Future Challenges
Fahad Siddiqui (NVIDIA Corporation, United Kingdom (Great Britain) & Queens University Belfast, United Kingdom (Great Britain)); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))
9:55 A Low-Cost Fault Injection Attack Resilient FSM Design
Ziming Wang (Harbin Institute of Technology (Shenzhen), China); Aijiao Cui (HIT Shenzhen, China); Gang Qu (University of Maryland, USA)

WS1: Special Session 1

SoDMA: System-Level Optimizations of Data Management for AI and Big Data Applications
Virtual Room 2
Chairs: Weiwen Jiang (University of Notre Dame, USA), Lei Yang (University of New Mexico, USA)
9:10 FPGA Based Co-Design of Storage-Side Query Filter for Big Data Systems
Jinyu Zhan, Ying Li and Wei Jiang (University of Electronic Science and Technology of China, China); Jianping Zhu (Tencent Technology Shenzhen Company of China, China)
9:25 Architectural Exploration on Racetrack Memories
Rui Xu, Edwin Sha, Qingfeng Zhuge, Liang Shi and Shouzhen Gu (East China Normal University, China)
9:40 A DNN Compression Framework for SOT-MRAM-Based Processing-In-Memory Engine
Geng Yuan, Xiaolong Ma, Sheng Lin and Zhengang Li (Northeastern University, USA); Jieren Deng and Caiwen Ding (University of Connecticut, USA)
9:55 Cube Attack on a Trojan-Compromised Hardware Implementation of Ascon
Basel Halak (Southampton University, United Kingdom (Great Britain)); Jorge Duarte-Sanchez (University of Southmpton, United Kingdom (Great Britain))

Wednesday, September 9 10:10 - 10:20

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Wednesday, September 9 10:20 - 11:05

WK1: Keynote1

Edge Computing Drives SoC Open Software Platforms
Jered Floyd, Member of Technical Staff, Technology Strategist, Red Hat, Inc.
Virtual Room 1
Chair: Jinjun Xiong (IBM T. J. Watson Research Center, USA)

Wednesday, September 9 11:05 - 11:10

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Wednesday, September 9 11:10 - 11:55

WK2: Keynote 2

Incorporation of Security into Chip Design Methodologies
Serge Leef, Program Manager, Microsystems Technology Office, DARPA
Virtual Room 1
Chair: Ramalingam Sridhar (University at Buffalo, USA)

Wednesday, September 9 11:55 - 12:00

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Wednesday, September 9 12:00 - 1:00

WP1: Poster Session 1

Virtual Room 3
Chair: Venkatesan Muthukumar (University of Nevada Las Vegas, USA)
12:00 The IANET Hardware Accelerator for Audio and Visual Data Classification
Rohini Jayachandre Gillela (Rochester Institute of Technology & RIT, USA); Amlan Ganguly, Dorin Patru and Mark Indovina (Rochester Institute of Technology, USA)
12:05 An Energy-Efficient Low Power LSTM Processor for Human Activity Monitoring
Arnab Neelim Mazumder and Hasib-Al Rashid (University of Maryland, Baltimore County, USA); Tinoosh Mohsenin (University of Maryland Baltimore County, USA)
12:10 Self-Correcting Op-Amp Input Offset Using Analog Floating Gates
Sai Nimmalapudi (UT Dallas, USA); Andrew Marshall (University of Texas at Dallas, USA); Harvey Stiegler (UT Dallas, USA); Keith Jarreau (Texas Instruments inc., USA)
12:15 Cycle-to-cycle Variation Enabled Energy Efficient Privacy Preserving Technology in ANN
Jingyan Fu (North Dakota State University, USA); Zhiheng Liao (NDSU, USA); Jinhui Wang (University of South Alabama, USA)
12:20 Improving the Performance of a NoC-based CNN Accelerator with Gather Support
Binayak Tiwari (University of Nevada Las Vegas, USA); Mei Yang (University of Nevada, Las Vegas, USA); Xiaohang Wang (South China University of Technology, China); Venkatesan Muthukumar (UNLV, USA); Yingtao Jiang (University of Nevada, Las Vegas, USA)
12:25 A Novel Method for Hardware Acceleration of Convex Hull Algorithm on Reconfigurable Hardware
Kris Min, Brenda Ly, Joshua Garner and Shahnam Mirzaei (California State University, Northridge, USA)
12:30 Trust in Machine Learning as a Service
Omid Aramoon (University of Maryland, USA)

WR2: Technical Session 2

DNN Acceleration
Virtual Room 1
Chairs: Yiyu Shi (University of Notre Dame, USA), Tianchen Wang (Norfolk Southern Corporation, USA)
12:00 Hardware Accelerator for Multi-Head Attention and Position-Wise Feed-Forward in the Transformer
Siyuan Lu, Meiqi Wang, Shuang Liang, Jun Lin and Zhongfeng Wang (Nanjing University, China)
12:15 Optimizing CNN Accelerator with Improved Roofline Model
Shaoxia Fang (Tsinghua University & Xilinx, Inc., China); Shulin Zeng and Yu Wang (Tsinghua University, China)
12:30 A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks
Taha Soliman (Bosch GmbH & University of Kaiserslautern, Germany); Ricardo Olivo, Maximilian Lederer and Thomas Kämpfe (Fraunhofer IPMS, Germany); Tobias Kirchner and Andre Guntoro (Bosch GmbH, Germany); Norbert Wehn (University of Kaiserslautern, Germany)
12:45 End-to-end Scalable and Low Power Multi-modal CNN for Respiratory-related Symptoms Detection
Haoran Ren (University of Maryland Baltimore County, USA); Arnab Neelim Mazumder and Hasib-Al Rashid (University of Maryland, Baltimore County, USA); Vandana Chandrareddy, Aidin Shiri and Tinoosh Mohsenin (University of Maryland Baltimore County, USA)

WS2: Special Session 2

Processing/Computing-in-Memory: From Circuit to Architecture, From Digital to Analog
Virtual Room 2
Chairs: Xiaoming Chen (Institute of Computing Technology, Chinese Academy of Sciences, China), Xunzhao Yin (Zhejiang University, China)
12:00 Analog Content Addressable Memory Using Ferroelectric: A Case Study of Search-In-Memory
Chuangtao Chen, Qingrong Huang, Chao Li and Li Andy Zhang (Zhejiang University, China); Cheng Zhuo (Zhejiang Univ, China); Xunzhao Yin (Zhejiang University, China)
12:15 C2IM: A Compact Computing-In-Memory Unit of 10 Transistors with Standard 6T SRAM
Fei Qiao (Tsinghua University, China); Erxiang Ren and Li Luo (Beijing Jiaotong University, China); Qi Wei and Zheyu Liu (Tsinghua University, China)
12:30 Processing-In-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency
Li Yang, Zhezhi He, Shaahin Angizi and Deliang Fan (Arizona State University, USA)
12:45 Deep Learning Acceleration Using Digital-Based Processing In-Memory
Mohsen Imani (University of California Irvine, USA); Saransh Gupta (UCSD, USA); Yeseong Kim (University of California San Diego, USA); Tajana Rosing (UCSD, USA)

Thursday, September 10

Thursday, September 10 9:00 - 10:00

TP2: Poster Session 2

Virtual Room 3
Chairs: Venkatesan Muthukumar (University of Nevada Las Vegas, USA), Md Tanvir Arafin (George Mason University, USA)
9:00 Switched Capacitor Based Area Efficient Voltage Quadruple for High Pumping Efficiency
Vikas Rana (STMicroelectronics Pvt. Ltd., India); Shivam Kalla (IIIT Delhi, India)
9:05 Mist-Scan: A Secure Scan Chain in Cryptographic Chips to Resist Scan-Based Attacks
Mohammad Taherifard, Hakem Beitollahi, Fateme Jamali and Amin Norollah (Iran University of Science and Technology, Iran); Ahmad Patooghy (University of Central Arkansas, USA)
9:10 DVFS Considering Spatial Correlation Timing and Process-Voltage-Temperature Variations
Tung-Liang Lin and Sao-Jie Chen (National Taiwan University, Taiwan)
9:15 A High-Speed Architecture for the Reduction in VDF Based on a Class Group
Yifeng Song, Danyang Zhu, Jing Tian and Zhongfeng Wang (Nanjing University, China)
9:20 An Inverter-based On-Chip Voltage Reference Generator for Low Power Application
Yuchen Zhao (Fudan University, China); Zhuo Zou (Fudan University & KTH Royal Institute of Technology, Sweden); Lirong Zheng (Fudan University, China)
9:25 Downlink-Centric User Scheduling for Full-Duplex MU-MIMO Systems
Jianhua Zhang, Ming Zou, Lai Wei, Meng Ma and Bingli Jiao (Peking University, China)
9:30 An Ultra-Low Power 900 MHz Intermediate Frequency Low Noise Amplifier for Low-Power RF Receivers
Aasish Boora, Kumar Thangarasu and Kiat Seng Yeo (Singapore University of Technology and Design, Singapore)
9:35 An Emergent Requirement of Approximate Computing: Data Security
Ye Wang (Harbin Institute of Technology, China)
9:40 A Data-Dependent Calibration Scheme for Non-Linearity of SAR ADC Using Neural Network
Hao-Wei Lu (Zhejiang University, China)

TR3: Technical Session 3

Configurable Design for DNN Acceleration
Virtual Room 1
Chair: Norbert Schuhmann (Fraunhofer IIS, Germany)
9:00 Efficient Inference of Large-Scale and Lightweight Convolutional Neural Networks on FPGA
Xiao Wu (Nanjing University, China); Yufei Ma (Peking University, China); Zhongfeng Wang (Nanjing University, China)
9:15 A Configurable FPGA Accelerator of Bi-LSTM Inference with Structured Sparsity
Shouliang Guo, Chao Fang, Jun Lin and Zhongfeng Wang (Nanjing University, China)
9:30 Dynamic Precision Multiplier for Deep Neural Network Accelerators
Chen Ding, Yuxiang Huan and Lirong Zheng (Fudan University, China); Zhuo Zou (Fudan University & KTH Royal Institute of Technology, Sweden)
9:45 Deep Reinforcement Learning for Self-Configurable NoC
Md Farhadur Reza (Eastern Illinois University, USA)

TS3: Special Session 3

3D Integrated Circuits
Virtual Room 2
Chairs: Mohamed Sabry (NTU, Egypt), Umamaheswara Tida (North Dakota State University, USA)
9:00 Energy-Efficient Adiabatic Circuits Using Transistor-Level Monolithic 3D Integration
Ivan Miketic and Emre Salman (Stony Brook University, USA)
9:15 Efficient Metal Inter-Layer via Utilization Strategies for Three-Dimensional Integrated Circuits
Umamaheswara Tida and Madhava Sarma Vemuri (North Dakota State University, USA)

Thursday, September 10 10:00 - 10:10

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Thursday, September 10 10:10 - 10:55

TK3: Keynote 3

Tiny Machine Learning on Microcontrollers
Song Han, Assistant Professor, MIT EECS
Virtual Room 1
Chairs: Danella Zhao (Old Dominion University, USA), Juergen Becker (Karlsruhe Institute of Technology, Germany)

Thursday, September 10 10:55 - 11:05

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Thursday, September 10 11:05 - 11:50

TK4: Keynote 4

miliJoules for 1000 Inferences: Machine Learning Systems "on the Cheap"
Diana Marculescu, Professor, University of Texas, Austin
Virtual Room 1
Chairs: Danella Zhao (Old Dominion University, USA), Juergen Becker (Karlsruhe Institute of Technology, Germany)

Thursday, September 10 11:50 - 12:00

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Thursday, September 10 12:00 - 1:00

TR4: Technical Session 4

FPGA and IoT Applications
Virtual Room 1
Chair: Andrew Marshall (University of Texas at Dallas, USA)
12:00 Achieving Flexible, Low-Latency and 100Gbps Line-rate Load Balancing over Ethernet on FPGA
Jinyu Xie, Wenbo Yin and Lingli Wang (Fudan University, China)
12:15 FABLE-DTS: Hardware-Software Co-Design of a Fast and Stable Data Transmission System for FPGAs
Jiabao Gao and Jian Wang (Fudan University, China); Md Tanvir Arafin (George Mason University, USA); Jinmei Lai (Fudan University, China)
12:30 Exploring the Scalability of OpenCL Coarse Grained Parallelism on Cloud FPGAs
Jhanani Thiagarajan (UNCC, USA); Arnab Ardhendu Purkayastha, Atul Patil and Hamed Tabkhi (University of North Carolina at Charlotte, USA)
12:45 Fine Grained Control Flow Checking with Dedicated FPGA Monitors
Augusto Hoppe and Juergen Becker (Karlsruhe Institute of Technology, Germany); Fernanda Kastensmidt (UFRGS, Brazil)

TS4: Special Session 4

Neuromorphic Computing - Opportunities and Challenges
Virtual Room 2
Chairs: Bipin Rajendran (King's College London, United Kingdom (Great Britain)), Abhronil Sengupta (Penn State University, USA)
12:00 Toward Scalable, Efficient, and Accurate Deep Spiking Neural Networks
Priyadarshini Panda (Yale University, USA)
12:15 Neuromorphic Computing Research at Intel: From Chip to Applications
Yulia Sandamirskaya (Intel Labs, Germany)
12:30 Re-Imagining System Design for Brain-Inspired Computing
Bipin Rajendran (King's College London, United Kingdom (Great Britain))
12:45 Spintronics Enabled Neuromorphic Computing: Hardware-Algorithm Co-Design
Abhronil Sengupta (Penn State University, USA)

Friday, September 11

Friday, September 11 9:00 - 10:00

FR5: Technical Session 5

Novel Circuit Designs
Virtual Room 1
Chair: Unni Chandran (Intel Corp., USA)
9:00 Hybrid Stochastic Computing Circuits in Continuous Statistics Domain
Renyuan Zhang (Nara Institute of Science and Technology, Japan); Tati Erlina (Universitas Andalas, Japan); Tinh Van Nguyen and Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
9:15 A Sub-1 ppm/°C CMOS Bandgap Voltage Reference with Process Tolerant Piecewise Second-Order Curvature Compensation
Yongjoon Ahn and Suhwan Kim (Seoul National University, Korea (South)); Hyunjoong Lee (Seoul National University & Gwanak Analog Co., Ltd., Korea (South))
9:30 Dynamic Supply and Threshold Voltage Scaling Towards Runtime Energy Optimization over a Wide Operating Performance Region
Shoya Sonoda (Kyoto University, Japan); Jun Shiomi (Osaka University, Japan); Hidetoshi Onodera (Kyoto University, Japan)
9:45 Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs
Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang and Hung-Ming Chen (National Chiao Tung University, Taiwan)

FS5: Special Session 5

Secure Your SoC: How to Design Unbreakable System-on-Chip (SoC)
Virtual Room 2
Chairs: Shivam Bhasin (Temasek Labs at NTU, Singapore), Anupam Chattopadhyay (Nanyang Technological University, Singapore)
9:00 Secure Your SoC: Building System-On-Chip Designs for Security
Shivam Bhasin (Temasek Labs at NTU, Singapore); Trevor E. Carlson (National University of Singapore, Singapore); Anupam Chattopadhyay and Vinay B. Y. Kumar (Nanyang Technological University, Singapore); Avi Mendelson (Computer Science Technion & Technion, Israel); Romain Poussier (Nanyang Technological University, Singapore); Yaswanth Tavva (National University of Singapore, Singapore)
9:15 Secure Integration of Untrusted SoC Components Through Hardware Root of Trust
Vinay B. Y. Kumar and Anupam Chattopadhyay (Nanyang Technological University, Singapore)

Friday, September 11 10:00 - 10:10

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Friday, September 11 10:10 - 10:55

FK5: Keynote 5

Quantum Systems - The foundation for a new model of computation
Christy Tyberg, Senior Manager, Quantum Hardware Technology Development IBM Quantum, IBM T. J. Watson Research Center
Virtual Room 1
Chairs: Thomas Buechner (IBM Germany Research & Development, Germany), Gang Qu (University of Maryland, USA)

Friday, September 11 10:55 - 11:05

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Friday, September 11 11:05 - 11:50

FK6: Keynote 6

ML-augmented Thermal Solution from Architecture to Layout for Large SoC and 3DIC
Norman Chang, Ansys Fellow & Chief Technologist, ANSYS, Inc.
Virtual Room 1
Chairs: Gang Qu (University of Maryland, USA), Jinjun Xiong (IBM T. J. Watson Research Center, USA)

Friday, September 11 11:50 - 12:00

Virtual Coffee Break

Rooms: Virtual Room 1, Virtual Room 2

Friday, September 11 12:00 - 1:00

FDT: Design Track

Virtual Room 2
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)
12:00 Simultaneous Multi Voltage Aware Timing Analysis Methodology for SOC Using Machine Learning
Vishant Gotra (INTEL Technology india pvt. ltd., India); Srinivasa Kodanda Rama Reddy (Intel Technology India Pvt. Ltd., India)
12:12 Optimized Power Grid Planning for Enabling Low Power Features for Leakage Power Reduction in SOC
Vishant Gotra (INTEL Technology india pvt. ltd., India); Srinivasa Kodanda Rama Reddy (Intel Technology India Pvt. Ltd., India); Tanniru Srinivasa Rao (Intel India Pvt Ltd, India); Pavithra P (Intel Technology India Pvt Ltd, India)
12:24 ASIC Power Estimation Across Revisions Using Machine Learning
Muhammad A Tariq (Intel Corporation & University of British Columbia, Canada); Howard Yang (Intel Corporation, Canada)
12:36 AutoML for Multilayer Perceptron and FPGA Co-design
Philip J Colangelo (Intel Corporation, USA); Oren Segal and Alexander Speicher (Hofstra University, USA); Martin Margala (University of Louisiana at Lafayette, USA)
12:48 Programmable Voltage Reference Circuit Using an Analog Floating Gate Device
Sai Nimmalapudi and Harvey Stiegler (UT Dallas, USA); Andrew Marshall (University of Texas at Dallas, USA); Keith Jarreau (Texas Instruments inc., USA)

FR6: Technical Session 6

Novel Design Methodologies
Virtual Room 1
Chair: Caiwen Ding (University of Connecticut, USA)
12:00 A Dynamic Expansion Order Algorithm for the SAT-based Minimization
Chia-Chun Lin, Kit Seng Tam, Chang-Cheng Ko, Hsin-Ping Yen and Sheng-Hsiu Wei (National Tsing Hua University, Taiwan); Yung-Chih Chen (National Taiwan University of Science and Technology, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan)
12:15 Holistic 2.5D Design Flow: A 65Nm Shared-Block Microcontroller Case Study
MD Arafat Kabir and Yarui Peng (University of Arkansas, USA)
12:30 A SpaceWire PHY with Double Data Rate and Fallback Redundancy
Mong Sim (University of Colorado Colorado Springs, USA); Yanyan Zhuang (University of Colorado, Colorado Springs, USA)
12:45 A Design Method for Delta-Sigma Force-Feedback Accelerometer Interface Systems
Mina Gad and Ahmed Elshennawy (Si-Ware Systems, Egypt); Ayman Hassan Ismail (Ain Shams University, Egypt)

Friday, September 11 1:00 - 1:10

FCR: Concluding Remarks

Virtual Room 1
Chair: Gang Qu (University of Maryland, USA)

Program last updated on no date/time given