Program for 2019 32nd IEEE International System-on-Chip Conference (SOCC)

Time Melati Main 4002 Melati Main 4003 Melati Main 4004 Melati Main Ballroom Session

Tuesday, September 3

09:00-10:30 Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory Tutorial 1B: AI Chip Technologies and DFT Methodologies      
10:30-10:50 Tea Break (Melati Main Foyer)      
10:50-12:20 Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory Tutorial 1B: AI Chip Technologies and DFT Methodologies      
12:20-13:40 Lunch (Melati Main Foyer)      
13:40-15:10 Tutorial 2A: Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test      
15:10-15:30 Tea Break (Melati Main Foyer)      
15:30-17:00 Tutorial 2A: Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test      

Wednesday, September 4

09:00-09:10       Opening Remarks  
09:10-09:20       Technical Program Overview  
09:20-10:10       Wednesday Keynote: The Memory Wall: Challenges and Solutions  
10:10-10:30 Tea Break (Melati Main 4102-4104)  
10:30-12:10 W1A: RF, Analog & Mixed Signal Circuits I W1B: New Dimensions in Network-on-Chip Design W1C: Special Session I: Energy Efficient Custom Computing with FPGAs    
12:10-13:30 Lunch (Melati Main 4102-4104)  
13:30-14:20       Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities  
14:20-14:40 Tea Break (Melati Main 4102-4104)  
14:40-16:00 W2A: Securing Your Chip W2B: Digital Signal Processing W2C: Special Session II: SoC Architecture and Circuit for IoT Applications-I    
16:00-16:20 Tea Break (Melati Main 4102-4104)  
16:20-18:00 W3A: Design Exploitation on Emerging Topics W3B: Wireline & Wireless Communication W3C: Special Session III: FPGA-based Processor for Intelligent Sensing    
18:30-20:00 WP: Poster Session & Reception WF: Ph.D. Forum

Thursday, September 5

09:00-09:50       Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power-Performance Adaptation Beyond Voltage Scaling  
09:50-10:40       Thursday Plenary: Anchoring Security in the Connected World  
10:40-11:00 Tea Break (Melati Main 4102-4104)  
11:00-12:20 T1A: Intelligent Design for Edge Computing T1B: Design Optimization for Approximate Computing T1C: Special Session IV: eNVM based In-Memory Computing for Intelligent and Secure SoCs    
12:20-13:30 Lunch (Melati Main 4102-4104)  
13:30-15:10 T2A: Low Power Design T2B: System Level Design Optimization T2C: Special Session V: Hardware Security    
15:10-15:30 Tea Break (Melati Main 4102-4104)  
15:30-17:00       Panel Discussion: Machine Learning & IoT: Which is the Enabler?  
18:00-21:00 Banquet Dinner with Show  

Friday, September 6

09:00-10:20 F1A: Design Track F1B: Special Session VI: SoC Architecture and Circuit for IoT Applications-II      
10:20-10:40 Tea Break      
10:40-12:00 F2A: RF, Analog and Mixed-signal Circuits II F2B: Special Session VII: Integrated Wearable Electromagnetic-Acoustics Sensing Circuits and Systems Towards SoC Chip Integration      
12:00-12:10 Closing Remarks      

Tuesday, September 3

Tuesday, September 3 9:00 - 10:30

Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory

Tony Kim Tae Hyoung, Nanyang Technological University, Singapore

Tutorial 1B: AI Chip Technologies and DFT Methodologies

Yu Huang and Rahul Singhal, Mentor Graphics, USA

Tuesday, September 3 10:30 - 10:50

Tea Break (Melati Main Foyer)

Tuesday, September 3 10:50 - 12:20

Tutorial 1A: Design of ultra-low power SRAM for IoT, security and computation-in-memory

Tony Kim Tae Hyoung, Nanyang Technological University, Singapore

Tutorial 1B: AI Chip Technologies and DFT Methodologies

Yu Huang and Rahul Singhal, Mentor Graphics, USA

Tuesday, September 3 12:20 - 13:40

Lunch (Melati Main Foyer)

Tuesday, September 3 13:40 - 15:10

Tutorial 2A: Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research

Ahmed Abelgawad, Central Michigan University, USA

Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test

Manoj Sachdev, University of Waterloo, Canada

Tuesday, September 3 15:10 - 15:30

Tea Break (Melati Main Foyer)

Tuesday, September 3 15:30 - 17:00

Tutorial 2A: Internet of Things (IoT): Signals, Communications, Applications, Challenges, and Future Research

Ahmed Abelgawad, Central Michigan University, USA

Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test

Manoj Sachdev, University of Waterloo, Canada

Wednesday, September 4

Wednesday, September 4 9:00 - 9:10

Opening Remarks

Magdy Bayoumi, Gwee Bah Hwee, Conference General Chairs

Wednesday, September 4 9:10 - 9:20

Technical Program Overview

Danella Zhao, Arindam Basu, Technical Program Chairs

Wednesday, September 4 9:20 - 10:10

Wednesday Keynote: The Memory Wall: Challenges and Solutions

Prof. Dr.-Ing. Norbert Wehn, Technische Universität Kaiserslautern, Germany
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

Wednesday, September 4 10:10 - 10:30

Tea Break (Melati Main 4102-4104)

Wednesday, September 4 10:30 - 12:10

W1A: RF, Analog & Mixed Signal Circuits I

Chair: Anh Tuan DO (Institute of Microelectronics, A*STAR, Singapore)
10:30 A BJT-Based Temperature Sensor in 40 nm CMOS with ±0.8°C (3Σ) Untrimmed Inaccuracy
Tantan Zhang (Institute of Microelectronics, Agency of Science, Technology and Research (A*STAR), Singapore); Yuan Gao (Institute of Microelectronics, A*STAR, Singapore)
10:55 A Low-Voltage Sub-ns Pulse Integrated CMOS Laser Diode Driver for SPAD-based Time-of-Flight Rangefinding in Mobile Applications
Samuel Rigault (Institut des Nanotechnologies de Lyon & STMicroelectronics, France); Nicolas Moeneclaey (STMicroelectronics, France); Lioua Labrak (Nanotechnology Institute of Lyon, France); Ian O'Connor (Lyon Institute of NanoTechnology & Ecole Centrale de Lyon, France)
11:20 A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications
Ata Khorami (Sharif University of Technology, Iran); Manoj Sachdev (University of Waterloo, Canada); Mohammad Sharifkhani (Sharif University of Technology, Iran)
11:45 A 10-Bit Area-efficient Source Driver for Printed OLED Display
Xiaoyu Guo (Beijing University of Aeronautics and Astronautics, China); Hong Ge Li (Pofessor, China)

W1B: New Dimensions in Network-on-Chip Design

Chair: Ram Krishnamurthy (Intel Corporation, USA)
10:30 RCAS: Critical Load Based Ranking for Efficient Channel Allocation in Wireless NoC
Sidhartha Sankar Rout (Indraprastha Institute of Information Technology, Delhi (IIIT Delhi), India); Vaibhav Ishwarlal Chaudhari (Indraprastha Institute of Information Technology Delhi (IIIT Delhi), India); Suyog Bhimrao Patil (Indraprastha Institute of Information Technology Delhi, India); Sujay Deb (IIIT Delhi, India)
10:55 Power and Area Efficient Router with Automated Clock Gating for Neuromorphic Computing
Junran Pu (Nanyang Technological University, Singapore); Vishnu P. Nambiar (Institute of Microelectronics, A*STAR, Singapore); Aarthy Mani (Institute of Microelectronics, Singapore); Wang Ling Goh (Nanyang Technological University, Singapore); Anh Tuan DO (Institute of Microelectronics, A*STAR, Singapore)
11:20 Application Specific Instruction Processor for Dynamic Connection Allocation in TDM-NoCs
Seungseok Nam (Dresden University of Technology & Vodafone chair, Germany); Emil Matus (Dresden University of Technology, Germany); Gerhard P. Fettweis (Technische Universität Dresden, Germany)
11:45 A Network on Chip Adapter for Real-Time and Safety-Critical Applications
Fabian Kempf and Nidhi Anantharajaiah (Karlsruhe Institute of Technology, Germany); Leonard Masing (Karlsruhe Institute of Technology (KIT), Germany); Juergen Becker (Karlsruhe Institute of Technology, Germany)

W1C: Special Session I: Energy Efficient Custom Computing with FPGAs

Chair: Po-Tsang Huang (National Chiao Tung University, Taiwan)
10:30 Mixed-Signal Circuits and Architectures for Energy-Efficient In-Memory and In-Sensor Computation of Artificial Neural Networks
Bongjin Kim (Nanyang Technological University, Singapore)
10:50 An Operation-Minimized FPGA Accelerator Design by Dynamically Exploiting Sparsity in CNN Winograd Transform
Xinkai Di (Institute of Electronics, Chinese Academy of Sciences & University of Chinese Academy of Sciences, P.R. China); Hai-Gang Yang and Zhihong Huang (Institute of Electronics, Chinese Academy of Sciences & University of Chinese Academy of Sciences, China); Ning Mao (University of Chinese Academy of Sciences, China)
11:10 Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC
Weixiong Jiang (Shanghaitech University, China); Heng Yu (Dalian Maritime University, China); Yajun Ha (ShanghaiTech University, China)
11:30 Training Deep Neural Networks Using Posit Number System
11:50 A NAND Flash Endurance Prediction Scheme with FPGA-based Memory Controller System
Zhuo Chen, Yuqian Pan, Mingyang Gong and Haichun Zhang (Huazhong University of Science and Technology, China); Mingyu Zhang (Shenzhen Zhongkexunlian Technology, China); Zhenglin Liu (Huazhong University of Science and Technology, China)

Wednesday, September 4 12:10 - 13:30

Lunch (Melati Main 4102-4104)

Wednesday, September 4 13:30 - 14:20

Wednesday Plenary: Machine Learning and Hardware Security Technologies for the Nanoscale era: Challenges & Opportunities

Dr. Ram Kumar Krishnamurthy, Senior Research Director and Senior Principal Engineer, Intel Labs, USA
Chair: Danella Zhao (Old Dominion University, USA)

Wednesday, September 4 14:20 - 14:40

Tea Break (Melati Main 4102-4104)

Wednesday, September 4 14:40 - 15:55

W2A: Securing Your Chip

Chair: Yu Huang (Mentor Graphics, USA)
14:40 A Glitch Key-Gate for Logic Locking
De-Xuan Ji (National Tsing Hua University, Taiwan); Hsiao-Yu Chiang (National Tsing-Hua University, Taiwan); Chia-Chun Lin and Chia-Cheng Wu (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan)
15:05 A Novel Test Vector Generation Method for Hardware Trojan Detection
Anindan Mondal, Mahabub Hasan Mahalat and Suraj Mandal (NIT Durgapur, India); Suchismita Roy (NIT, Durgapur, India); Bibhash Sen (DS 9A NIT Durgapur & National Institute Of Technology - Durgapur, India)
15:30 Reconfigurable Routing Paths as Noise Generators Using NoC Platform for Hardware Security Applications
Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne and Kwen Siong Chong (Nanyang Technological University, Singapore); Bah Hwee Gwee (NTU, Singapore)

W2B: Digital Signal Processing

Chair: Arindam Basu (Nanyang Technological University, Singapore)
14:40 A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection
Guan-Min Luo and Ching-Yuan Yang (National Chung Hsing University, Taiwan)
15:05 Error-latency Trade-Off for Asynchronous Stochastic Computing with Sigma-Delta Streams for the IoT
Luisa P Gonzalez, Mircea Stan and Stephen G. Wilson (University of Virginia, USA)
15:30 Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function
Ming Ming Wong (Agency for Science, Technology and Research (A*STAR), Singapore); Anh Tuan DO (Institute of Microelectronics, A*STAR, Singapore)

Wednesday, September 4 14:40 - 16:00

W2C: Special Session II: SoC Architecture and Circuit for IoT Applications-I

Chair: Lan-Da Van (National Chiao Tung University, Taiwan)
14:40 An All-Digital Temperature Sensor with Process and Voltage Variation Tolerance for IoT Applications
Ching-Che Chung and Hsin-Han Huang (National Chung Cheng University, Taiwan)
15:00 ML-based Thermal Sensor Calibration by Bivariate Gaussian Mixture Model Estimation
Wei-Chien Kuo, Li-wei Liu, Yen-Chin Liao and Hsie-Chia Chang (National Chiao Tung University, Taiwan)
15:20 Pvalite CLN: Lightweight Object Detection with Classfication and Localization Network
Ching-Kan Tseng and Chi-Chi Tsai (National Chiao-Tung University, Taiwan); Jiun-In Guo (Department of Electronics Engineering, National Chiao-Tung University, Taiwan)
15:40 A Digital-Enhanced Interferometric Radar Sensor for Physiological Sign Monitoring
Zhongyuan Fang and Liheng Lou (Nanyang Technological University, Singapore)

Wednesday, September 4 16:00 - 16:20

Tea Break (Melati Main 4102-4104)

Wednesday, September 4 16:20 - 18:00

W3A: Design Exploitation on Emerging Topics

Chair: Kun-Chih Chen (National Sun Yat-Sen University, Taiwan)
16:20 Dimension Reduction for Efficient Pattern Recognition in High Spatial Resolution Data Using Quantum Algorithms
Naveed Mahmud and Esam El-Araby (University of Kansas, USA)
16:45 DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon
Renyuan Zhang (Nara Institute of Science and Technology, Japan); Yan Chen (Nara Advanced Institute of Science and Technology, Japan); Takashi Nakada (NAIST, Japan); Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan)
17:10 Loop Optimizations of MGS-QRD Algorithm for FPGA High-Level Synthesis
Chong Yeam Tan and Chia Yee Ooi (Universiti Teknologi Malaysia, Malaysia); Nordinah Ismail (Universiti Teknologi Malaysia (UTM), Malaysia)
17:35 An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks
Duy-Anh Nguyen (VNU University of Engineering and Technology, Vietnam); Francesca Iacopi (University of Technology Sydney, Vietnam); Xuan-Tu Tran (VIetnam National University, Hanoi, Vietnam)

W3B: Wireline & Wireless Communication

Chair: Sujay Deb (IIIT Delhi, India)
16:20 A 45 Gb/s, 98 fJ/bit, 0.02 Mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-Nm CMOS
Akira Tsuchiya (The University of Shiga Prefecture, Japan); Akitaka Hiratsuka (Kyoto University, Japan); Kenji Tanaka (NTT Device Technology Labs, NTT Corporation, Japan); Hiroyuki Fukuyama (NTT Device Technology Labs, NTT Corporation); Naoki Miura (NTT Device Technology Labs, NTT Corporation, Japan); Hideyuki Nosaka (NTT Device Technology Labs, NTT Corporation); Hidetoshi Onodera (Kyoto University, Japan)
16:45 Group Delay Compensation by Combining 3-Tap FFE with CTLE for 80Gbps-PAM4 Optical Transmitter
Jiquan Li (Southeast University, China); Ying mei Chen (SEU, China); Zhen Zhang, Hui Wang, Chao Guo and Binbin Yang (Southeast University, China)
17:10 Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier
Shinya Tanimura (University of Shiga Prefecture, Japan); Akira Tsuchiya (The University of Shiga Prefecture, Japan); Ryosuke Noguchi (University of Shiga Prefecture, Japan); Toshiyuki Inoue and Keiji Kishine (The University of Shiga Prefecture, Japan)
17:35 A Quad Linear 56Gbaud PAM4 Transimpedance Amplifier in 0.18Um SiGe BiCMOS Technology
Hui Wang (Southeast University, China); Ying mei Chen, Yuan Gao and Lin Li (SEU, China); Zhen Zhang, Chao Guo and Jiquan Li (Southeast University, China)

W3C: Special Session III: FPGA-based Processor for Intelligent Sensing

Chairs: Wang Chao (Huazhong University of Science and Technology, China), Jun Zhou (University of Electronic Science and Technology of China, China)
16:20 A 4K Vision Computing Platform with Convolutional Neural Network Engine on FPGA
Ke Xu (ZTE Microelectronics Research Institute, China); Fang Zhu (ZTE Corporation, China); Xiao Zhang, Bin Han, Jiewei Xiao, Hong Wang, Dehui Kong, Zhou Han, Degen Zhen, Guoning Lu, Jisong Ai, Xin Liu and Zhi Huang (ZTE Microelectronics Research Institute, China)
16:45 A Minimal Adder-oriented 1D DST-VII/DCT-VIII Hardware Implementation for VVC Standard
Yixuan Zeng (Fudan University, China); Heming Sun and Jiro Katto (Waseda University, Japan); Xiaoyang Zeng (Fudan University, China); Yibo Fan (State Key Lab of ASIC and System, Fudan University, China)
17:10 A Power-Efficient Programmable DCNN Processor for Intelligent Sensing
Bo Wang, Jiayan Gan, Yuxiang Xie and Yin Wang (University of Electronic Science and Technology of China, China); Zhuoling Xiao (University of Oxford, United Kingdom (Great Britain)); Jun Zhou (University of Electronic Science and Technology of China, China)
17:35 FPGA-based Object Detection Processor with HOG Feature and SVM Classifier
Fengwei An, Peng Xu and Zhihua Xiao (Southern University of Science and Technology, China); Wang Chao (Huazhong University of Science and Technology, China)

Wednesday, September 4 18:30 - 20:00

WF: Ph.D. Forum

Chair: Danella Zhao (Old Dominion University, USA)
Efficient Hardware Acceleration of Convolutional Neural Networks
Kala S (Cochin University of Science And Technology, India); Babita R. Jose (Cochin University of Science and Technology, India); Jimson Mathew (IIT Patna & Computer Science Dept, India); Nalesh S (CUSAT, India)
Synthesis of Linear and Non-linear Analog Circuits
Debanjana Datta (IIEST, Shibpur, India); Baidyanath Ray (Indian Institute of Engineering, Science and Technology, Shibpur, India); Ayan Banerjee (Indian Institute of Engineering Science and Technology, India)
Reactive and Proactive Threat Detection and Prevention for the Internet of Things
Matthew Hagan (Queens University Belfast, United Kingdom (Great Britain)); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain)); Kieran McLaughlin (Queen's University Belfast, United Kingdom (Great Britain))

WP: Poster Session & Reception

Chair: Danella Zhao (Old Dominion University, USA)
A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises
Yan-Ping Chang (National Tsing Hua University, Taiwan); Teng-Chia Wang (National TSING HUA University, Taiwan); Yun-Ju Lee and Chia-Chun Lin (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Chun-Yao Wang (National Tsing Hua University, Taiwan)
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration
Florian Oszwald (BMW Group, Germany); Philipp Obergfell (BMW Group Research, New Technologies, Innovations, Germany); Matthias Traub (BMW Group, Germany); Juergen Becker (Karlsruhe Institute of Technology, Germany)
A 100 KS/s 8-10 Bit Resolution-Reconfigurable SAR ADC for Bioelectronics Application
Yunfeng Hu (University of Electronic Science and Technology of China, Zhongshan Institute, China); Lisheng Chen (University of Electronic Science and Technology of China, Zhongshan Institute, Hong Kong); Hui Chen, Yi Wen, Huabin Zhang and Xiaojia Liu (University of Electronic Science and Technology of China, Zhongshan Institute, China)
Energy-Aware Workload Allocation for Distributed Deep Neural Networks in Edge-Cloud Continuum
Yi Jin, Jiawei Xu, Yuxiang Huan, Yulong Yan and Lirong Zheng (Fudan University, China); Zhuo Zou (Fudan University & KTH Royal Institute of Technology, Sweden)
Establishing Cyber Resilience in Embedded Systems for Securing Next-Generation Critical Infrastructure
Fahad Siddiqui (Queens University Belfast & The Centre for Secure Information Technologies (CSIT), United Kingdom (Great Britain)); Matthew Hagan (Queens University Belfast, United Kingdom (Great Britain)); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))
Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images
Sai Praveen Kadiyala (Nanyang Technological University, Singapore); Vikram Kumar Pudi (Indian Institute of Technology, Tirupati, India); Mohit Garg (Birla Institute of Technology and Science (BITS) Pilani, India); Hau Ngo (United States Naval Academy, USA); Siew Kei Lam and Srikanthan Thambipillai (Nanyang Technological University, Singapore)
Efficient Router Architecture for Trace Reduction During NoC Post-Silicon Validation
Sidhartha Sankar Rout (Indraprastha Institute of Information Technology, Delhi (IIIT Delhi), India); Suyog Bhimrao Patil (Indraprastha Institute of Information Technology Delhi, India); Vaibhav Ishwarlal Chaudhari (Indraprastha Institute of Information Technology Delhi (IIIT Delhi), India); Sujay Deb (IIIT Delhi, India)
Timing Aware Wrapper Cells Reduction for Pre-bond Testing in 3D-ICs
Pei-An Ho, Yen-Hao Chen, Allen Wu and TingTing Hwang (National Tsing Hua University, Taiwan)
Coverage Driven Verification Methodology for Asynchronous Neuromorphic Routers
Yun Kwan Lee (Agency for Science, Technology and Research & Institute of Microelectronics, Singapore); Vishnu P. Nambiar (Institute of Microelectronics, A*STAR, Singapore); Junran Pu and Wang Ling Goh (Nanyang Technological University, Singapore); Anh Tuan DO (Institute of Microelectronics, A*STAR, Singapore)
28Nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications
Po-Tsang Huang and Huan-Jan Tseng (National Chiao Tung University, Taiwan); Shang-Lin Wu (Nation Chiao Tung University, Taiwan); Wei-Chang Wang and Sheng-Chi Lung (Faraday Technology Corporation, Taiwan); Wei Hwang and Ching-Te Chuang (National Chiao Tung University, Taiwan)
Runtime Packet-Dropping Detection of Faulty Nodes in Network-on-Chip
Luka Daoud and Nader Rafla (Boise State University, USA)
Accelerating Binary-Matrix Multiplication on FPGA
Debjyoti Bhattacharjee, Anupam Chattopadhyay and Ricardo Liwongan (Nanyang Technological University, Singapore)
LIGHTER-R: Optimized Reversible Circuit Implementation for SBoxes
Vishnu Asutosh Dasu (Manipal Institute of Technology, India); Anubhab Baksi (School of Computer Science & Engineering, Nanayang Technological University, Singapore); Sumanta Sarkar (TCS Innovation Labs, India); Anupam Chattopadhyay (Nanyang Technological University, Singapore)
N2OC: Neural-Network-on-Chip Architecture
Kasem Khalil, Omar Eldash, Ashok Kumar and Magdy Bayoumi (University of Louisiana at Lafayette, USA)
Current-Reuse LC Divide-by-8 Injection-Locked Frequency Divider
Wen Cheng Lai and Sheng-Lyang Jang (National Taiwan University of Science and Technology, Taiwan)
A 90µW, 2.5GHz High Linearity Programmable Delay Cell for Signal Duty-Cycle Adjustment
Tobias Schirmer, Mahdi Khafaji, Jan Pliva and Frank Ellinger (Technische Universität Dresden, Germany)
A 2.7-Gb/s Clock and Data Recovery Circuit Based on D/PLL
You-Sheng Lin, Miao-Shan Li and Ching-Yuan Yang (National Chung Hsing University, Taiwan)
Analysis and Modeling of Passive LC Filters Using Node Elimination Technique
Sotoudeh Hamedi-Hagh (San Jose State University, USA)
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s
Johannes Pfau (Karlsruhe Institute of Technology, Germany); Maximilian Reuter (TU Darmstadt, Germany); Tanja Harbaum (Karlsruhe Institute of Technology, Germany); Klaus Hofmann (TU Darmstadt, Germany); Juergen Becker (Karlsruhe Institute of Technology, Germany)
Acceleration of Polynomial Matrix Multiplication on Zynq-7000 System-on-Chip
Server Kasap (University of Essex & Intelligent Embedded Systems and Environments, United Kingdom (Great Britain)); Soydan Redif (European University of Lefke, Turkey); Eduardo Wachter (University of Essex, United Kingdom (Great Britain))
Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array
Hirotoshi Ito and Minoru Watanabe (Shizuoka University, Japan)

Thursday, September 5

Thursday, September 5 9:00 - 9:50

Thursday Keynote: Survival of The Fittest: Circuits and Architectures for Computation with Wide Power-Performance Adaptation Beyond Voltage Scaling

Prof. Massimo Alioto, National University of Singapore, Singapore
Chair: Magdy Bayoumi (University of Louisiana at Lafayette, USA)

Thursday, September 5 9:50 - 10:40

Thursday Plenary: Anchoring Security in the Connected World

Jerome Tija, Senior Director, Head of Development Centre Infineon Technologies Asia Pacific Pte Ltd

Thursday, September 5 10:40 - 11:00

Tea Break (Melati Main 4102-4104)

Thursday, September 5 11:00 - 12:15

T1A: Intelligent Design for Edge Computing

Chair: Mircea Stan (University of Virginia, USA)
11:00 0.8 BER 1.2 pJ/bit Arbiter-based PUF for Edge Computing Using Phase-Difference Accumulation Technique
Anh Tuan DO (Institute of Microelectronics, A*STAR, Singapore)
11:25 EBBIOT: A Low-complexity Tracking Algorithm for Surveillance in IoVT Using Stationary Neuromorphic Vision Sensors
Jyotibdha Acharya (Nanyang Technological University, Singapore); Andres Ussa Caycedo (National University of Singapore, Singapore); Vandana Reddy Padala and Rishi Raj Sidhu Singh (Nanyang Technological University, Singapore); Garrick Orchard and Bharath Ramesh (National University of Singapore, Singapore); Arindam Basu (Nanyang Technological University, Singapore)
11:50 An Efficient Implementation of Arbiter PUF on FPGA for IoT Application
Mahabub Hasan Mahalat, Suraj Mandal and Anindan Mondal (NIT Durgapur, India); Bibhash Sen (DS 9A NIT Durgapur & National Institute Of Technology - Durgapur, India)

T1B: Design Optimization for Approximate Computing

Chairs: Esam El-Araby (University of Kansas, USA), Michiko Inoue (Nara Institute of Science and Technology, Japan)
11:00 Energy-Efficient and High-Speed Approximate Signed Multipliers with Sign-Focused Compressors
Yi Guo, Heming Sun and Shinji Kimura (Waseda University, Japan)
11:25 Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs
Toan Van Nguyen and Jeong-Gun Lee (Hallym University, Korea)
11:50 Fused Multiply-Add for Variable Precision Floating-Point
Alberto Nannarelli (Technical University of Denmark, Denmark)

Thursday, September 5 11:00 - 12:20

T1C: Special Session IV: eNVM based In-Memory Computing for Intelligent and Secure SoCs

Chair: Kejie Huang (Zhejiang University, China)
11:00 eNVM Based In-memory Computing for Intelligent and Secure Computing Systems
Kejie Huang and Chuyun Qin (Zhejiang University, China)
11:20 Enabling Neuromorphic Computing: BEOL Integration of CMOS RRAM Chip and Programmable Performance
Weijie Wang (Institute of Microelectronics, Agency for Science, Technology and Research, Singapore); Victor Yiqian Zhuo, Zhixian Chen, Hock Koon Lee, Minghua Li and Wendong Song (Institute of Microelectronics, Agency of Science, Technology and Research, Singapore)
11:40 ReRAM Non-Volatile AES Encryption Engine for IoT Application
Li Fei (Institute of Microelectronics & Singapore, Singapore); Jayce Lay Keng Lim (Institute of Microelectronics, Singapore)
12:00 Co-Design of Highly Uniform ReRAM Arrays in 180Nm CMOS Technology for Neuromorphic Systems
Victor Yiqian Zhuo (Institute of Microelectronics, Agency of Science, Technology and Research, Singapore); Weijie Wang (Institute of Microelectronics, Agency for Science, Technology and Research, Singapore); Zhixian Chen, Hock Koon Lee, Minghua Li and Wendong Song (Institute of Microelectronics, Agency of Science, Technology and Research, Singapore)

Thursday, September 5 12:20 - 13:30

Lunch (Melati Main 4102-4104)

Thursday, September 5 13:30 - 15:10

T2A: Low Power Design

Chair: Alberto Nannarelli (Technical University of Denmark, Denmark)
13:30 Voltage Stacked Design of a Microcontroller for near/sub-threshold Operation
Kamlesh Singh and Barry De Bruin (Eindhoven University of Technology, The Netherlands); Jos Huisken (University of Technology Eindhoven, Netherlands, The Netherlands); Hailong Jiao (Peking University Shenzhen Graduate School, China); Jose de Gyvez (Eindhoven University of Technology, The Netherlands)
13:55 Dynamic Supply Voltage Level Generation for Minimum Energy Real Time Tasks Using Geometric Programming
Manohara H t and B p Harish (UVCE & Bangalore University, India)
14:20 ML-based Reinforcement Learning Approach for Power Management in SoCs
David Akselrod (Advanced Micro Devices, Canada)
14:45 A Speed and Energy Focused Framework for Dynamic Hardware Reconfiguration
Omar Eldash, Kasem Khalil, Ashok Kumar and Magdy Bayoumi (University of Louisiana at Lafayette, USA)

T2B: System Level Design Optimization

Chair: Kevin Fong (National University of Singapore, Singapore)
13:30 Learning of Multi-Dimensional Analog Circuits Through Generative Adversarial Network (GAN)
Salahuddin Raju (Scientist, Singapore); Rahul Dutta (Principal Research Engineer, Singapore); Ashish James (A*STAR, Singapore); Chemmanda John Leo (Scientist, Singapore); Yong-Joon Jeon (Institute of Microelectronics, A*STAR, Singapore); Balagopal Unnikrishnan (National Universtity of Singapore, Singapore); Chuan Sheng Foo (Institute for Infocomm Research, Singapore); Zeng Zeng (A*STAR, Singapore); Kevin Chai Tshun Chuan (Scientist, Singapore); Vijay Chandrasekhar (Institute for Infocomm Research, Singapore)
13:55 Crosstalk-aware TSV-buffer Insertion in 3D IC
Yen-Hao Chen, Po-Chen Huang, Fu-Wei Chen, Allen Wu and TingTing Hwang (National Tsing Hua University, Taiwan)
14:20 Register Requirement Minimization of Fixed-Depth Pipelines for Streaming Data Applications
Thomas Goldbrunner, Nguyen Anh Vu Doan, Diogo Poças, Thomas Wild and Andreas Herkersdorf (Technical University of Munich, Germany)
14:45 Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem
Riaz-Ul-Haque Mian, Michihiro Shintani and Michiko Inoue (Nara Institute of Science and Technology, Japan)

T2C: Special Session V: Hardware Security

Chair: Avi Mendelson (Computer Science Technion & Technion, Israel)
13:30 ITUS: A Secure RISC-V System-on-Chip
Vinay B. Y. Kumar and Anupam Chattopadhyay (Nanyang Technological University, Singapore); Jawad Haj-Yahya (A-Star, Singapore); Avi Mendelson (Computer Science Technion & Technion, Israel)
13:55 Protecting the Integrity of Processor Cores with Logic Encryption
Dominik Šišejković, Farhad Amirali Merchant and Rainer Leupers (RWTH Aachen University, Germany)
14:20 Secure Speculative Core
Avi Mendelson (Computer Science Technion & Technion, Israel)
14:45 MSMPX: Microarchitectural Extensions for Meltdown Safe Memory Protection
Gnanambikai Krishnakumar and Chester D. Rebeiro (Indian Institute of Technology Madras, India)

Thursday, September 5 15:10 - 15:30

Tea Break (Melati Main 4102-4104)

Thursday, September 5 15:30 - 17:00

Panel Discussion: Machine Learning & IoT: Which is the Enabler?

Jurgen Becker (Karlsruhe Institute of Technology) , Massimo Alioto (National Univ. of Singapore), Jerome Tjia (Infineon Tech), Mircea Stan (Univ. of Virginia)
Chair: Magdy Bayoumi (University of Louisiana at Lafayette, USA)

Thursday, September 5 18:00 - 21:00

Banquet Dinner with Show

Friday, September 6

Friday, September 6 9:00 - 10:20

F1A: Design Track

Chairs: Thomas Buechner (IBM Germany Research & Development, Germany), Li Fei (Institute of Microelectronics & Singapore, Singapore)
9:00 Scalable Physical Design Approach for Many-core Neuromorphic System-on-Chip
Aarthy Mani (Institute of Microelectronics, Singapore); Vishnu P. Nambiar and Anh Tuan DO (Institute of Microelectronics, A*STAR, Singapore); Bin Zhao (IME, Singapore)
9:20 14.5 GHz Clock Custom Digital Design Methodology Utilizing Back Bias Tuning Capability in 22Nm FD-SOI CMOS Technology
9:40 Integration of Safety Related IP's into SoC's - Challenges and Mitigations
Shivakumar Chonnad (Synopsys Inc, USA); Vladimir Litovtchenko (Synopsys GmbH, Germany)
10:00 Embedded 6-T SRAM with Novel Self-Adaptive Write Enhance Scheme for Improved Fmax
Vijit Gadi (Synopsys Inc, India); Kunjan Bhatt and Sanjay Yadav (Synopsys, India)

Friday, September 6 9:00 - 10:15

F1B: Special Session VI: SoC Architecture and Circuit for IoT Applications-II

Chairs: Kwen Siong Chong (Nanyang Technological University, Singapore), Lan-Da Van (National Chiao Tung University, Taiwan)
9:00 Scalable DU Architecture for IoT Massive Connection
Kuohua Sung (National Chaio Tung University, Taiwan); Terngyin Hsu (NCTU, Taiwan)
9:25 A Neural-Network-Based Non-linear Interference Cancellation Scheme for Wireless IoT Backhaul with Dual-Connectivity
Huiliang Zhang and Zhonglong Wang (Peking University, China); Fei Qin (vivo Mobile Communication Technology Co., Ltd, Beijing, China); Meng Ma and Jianhua Zhang (Peking University, China)
9:50 High-Efficiency Step-Down Multi-Mode Switching DC-DC Converter for IoT Devices
Hsiang-Ming Yen (National Chiao Tung University, Taiwan); Chia-Ling Wei (National Cheng Kung University, Taiwan); Chi-Shi Chen (National Chip Implementation Center, Taiwan)

Friday, September 6 10:20 - 10:40

Tea Break

Friday, September 6 10:40 - 11:55

F2A: RF, Analog and Mixed-signal Circuits II

Chair: Andrew Marshall (University of Texas at Dallas, USA)
10:40 Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits
Debanjana Datta (IIEST, Shibpur, India); Mousumi Bhanja (CVRCE, Bhubaneswar, India); Anirban Chaudhuri (IIEST, Shibpur, India); Baidyanath Ray (Indian Institute of Engineering, Science and Technology, Shibpur, India); Ayan Banerjee (Indian Institute of Engineering Science and Technology, India)
11:05 A Digitally Controllable Passive Variable Slope Gain Equalizer for Wideband Radio Frequency System-on-Chip Applications
Sreekesh Lakshminarayanan and Klaus Hofmann (Technische Universität Darmstadt)
11:30 A 100-mVpp Input Range 10-kHz BW VCO-based CT-DSM Neuro-Recording IC in 40-Nm CMOS
Wei Zhou and Wang Ling Goh (Nanyang Technological University, Singapore); Yi Chen (Beijing Academy of Edge Computing, China); Tantan Zhang (Institute of Microelectronics, Agency of Science, Technology and Research (A*STAR), Singapore); Yuan Gao (Institute of Microelectronics, A*STAR, Singapore)

Friday, September 6 10:40 - 12:00

F2B: Special Session VII: Integrated Wearable Electromagnetic-Acoustics Sensing Circuits and Systems Towards SoC Chip Integration

Chairs: Ramalingam Sridhar (University at Buffalo, USA), Ming Ming Wong (Agency for Science, Technology and Research (A*STAR), Singapore)
10:40 Radar Transceivers for Inverse Synthetic Aperture Radar (ISAR) Imaging of Human Activity in 65Nm CMOS
Liheng Lou and Zhongyuan Fang (Nanyang Technological University, Singapore)
11:00 A Lossless Astronomical Data Compression Scheme with FPGA Acceleration
Yu Zheng (Shanghai Jiao Tong University, China); Yongxin Zhu (Chinese Academy of Sciences & Shanghai Jiao Tong University, China); Yuefeng Song, Tianhao Nan and Wanyi Li (Shanghai Jiao Tong University, China)
11:20 AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design
Wenfeng Zhao (University of Minnesota, USA); Biao Sun (Tianjin University, China); Jian Chen and Yajun Ha (ShanghaiTech University, China)
11:40 A Low Power Analog Front-end for Ultrasound Receiver
Chuanshi Yang and Zhongyuan Fang (Nanyang Technological University, Singapore)

Friday, September 6 12:00 - 12:10

Closing Remarks

Magdy Bayoumi, Gwee Bah Hwee, Conference General Chairs