Program for 2018 31st IEEE International System-on-Chip Conference (SOCC)

Time Salon D Salon E Salon F Session

Tuesday, September 4

09:00-10:30 Tutorial 1A: Thermal- and Reliability-Aware Design in Nanometer Technologies Tutorial 1B: The Good, The Bad, and The Potential, A Tutorial for the Adversarial Attacks  
10:30-10:50 Break
10:50-12:20 Tutorial 1A: Thermal- and Reliability-Aware Design in Nanometer Technologies Tutorial 1C: IoT Security: - Threats, Security Challenges and IoT Security Research and Technology Trends  
12:20-13:40 Lunch
13:40-15:10 Tutorial 2A: Benchmarking of Advanced CMOS and beyond CMOS circuits Tutorial 2B: Ultra-Low Power System Optimization & Energy Harvesting Opportunities  
15:10-15:30 Break
15:30-17:00 Tutorial 2A: Benchmarking of Advanced CMOS and beyond CMOS circuits Tutorial 2B: Ultra-Low Power System Optimization & Energy Harvesting Opportunities  

Wednesday, September 5

09:00-09:10 Opening Remarks    
09:10-09:20 Technical Program Overview    
09:20-10:10 Wednesday Keynote    
10:10-10:30 Break
10:30-12:10 W1A: Low Power Design W1B: RF Circuits  
12:10-13:30 Lunch
13:30-14:20 Wednesday Plenary    
14:20-14:40 Break
14:40-16:20 W2A: Emerging and Evolutionary Design W2B: High Performance Low Power Circuits  
16:20-18:00 W3A: Security W3B: Reconfigurable Architectures and Applications  
18:00-20:00     WP: Poster Session & Reception  

Thursday, September 6

09:00-09:50 Thursday Keynote    
09:50-10:40 Thursday Morning Plenary    
10:40-11:00       Break
11:00-12:15 T1A: Memory Circuits and Applications T1B: Digital and Mixed-Signal Circuits  
12:15-13:30 Lunch
13:30-14:20 Thursday Afternoon Plenary    
14:20-14:40 Break
14:40-16:45 T2A: Special Session: ML/AI in Startups and Government Agencies T2B: Design Track  
16:45-18:00 Panel Discussion: ML/AI in Startups and Government Agencies    
18:30-21:00 Banquet with Banquet Speech

Friday, September 7

09:00-10:15 F1A: MPSoC and Design Methodologies I F1B: Low Power Circuits I  
10:15-10:35 Break
10:35-11:50 F2A: MPSoC and Design Methodologies II F2B: Low Power Circuits II  
11:50-12:00 Closing Remarks    

Tuesday, September 4

Tuesday, September 4 9:00 - 10:30

Tutorial 1A: Thermal- and Reliability-Aware Design in Nanometer TechnologiesDetails

Mircea Stan, University of Virginia
Rooms: Salon D, Salon E

Tutorial 1B: The Good, The Bad, and The Potential, A Tutorial for the Adversarial AttacksDetails

Xiang Chen, George Mason University
Room: Salon F

Tuesday, September 4 10:30 - 10:50

Break

Tuesday, September 4 10:50 - 12:20

Tutorial 1A: Thermal- and Reliability-Aware Design in Nanometer TechnologiesDetails

Mircea Stan, University of Virginia
Rooms: Salon D, Salon E

Tutorial 1C: IoT Security: - Threats, Security Challenges and IoT Security Research and Technology TrendsDetails

Sakir Sezer, Queen's University, Belfast
Room: Salon F

Tuesday, September 4 12:20 - 13:40

Lunch

Tuesday, September 4 13:40 - 15:10

Tutorial 2A: Benchmarking of Advanced CMOS and beyond CMOS circuitsDetails

Andrew Marshall, UT Dallas
Rooms: Salon D, Salon E

Tutorial 2B: Ultra-Low Power System Optimization & Energy Harvesting OpportunitiesDetails

Brian Zahnstecher, PowerRox LLC
Room: Salon F

Tuesday, September 4 15:10 - 15:30

Break

Tuesday, September 4 15:30 - 17:00

Tutorial 2A: Benchmarking of Advanced CMOS and beyond CMOS circuitsDetails

Andrew Marshall, UT Dallas
Rooms: Salon D, Salon E

Tutorial 2B: Ultra-Low Power System Optimization & Energy Harvesting OpportunitiesDetails

Brian Zahnstecher, PowerRox LLC
Room: Salon F

Wednesday, September 5

Wednesday, September 5 9:00 - 9:10

Opening Remarks

Helen Li, Massimo Alioto, SOCC 2018 Conference Chairs
Rooms: Salon D, Salon E

Wednesday, September 5 9:10 - 9:20

Technical Program Overview

Mircea Stan, Karan Bhatia, SOCC 2018 Technical Program Chairs
Rooms: Salon D, Salon E

Wednesday, September 5 9:20 - 10:10

Wednesday KeynoteDetails

Meeting the Hyper Growth Challenge of AI Applications
Fadi Azhari, VP of marketing, Wave Computing
Rooms: Salon D, Salon E
Chair: Mircea Stan (University of Virginia, USA)

Organizations today looking to accelerate their AI and deep learning applications must make significant compromises in performance, price and ease of use due to the limited capabilities of traditional hardware solutions, which only address a narrow set of requirements for very specific needs. For example, they have to use multiple solutions for a single AI application, or they need to use different implementations for different types of data sets. This has created "silos" of different hardware architectures, making the extraction of intelligence from data difficult to manage, provision and scale to meet the hyper growth of AI applications.

In this presentation, Wave Computing VP of Marketing Fadi Azhari will explain how the lack of a common AI platform, from the datacenter to the edge, is slowing AI market growth and reducing the productivity of data scientists in a wide range of fields. He will also explain how Wave Computing is addressing this challenge, and enabling data scientists to experiment, develop, test and deploy neural networks on a common platform spanning to the Edge of Cloud - and enabling enterprise-class companies better leverage AI as a fundamental part of their digital strategies.

Wednesday, September 5 10:10 - 10:30

Break

Wednesday, September 5 10:30 - 12:10

W1A: Low Power Design

Rooms: Salon D, Salon E
Chair: Ram Krishnamurthy (Intel Corporation, USA)
10:30 On a New Hardware Trojan Attack on Power Budgeting of Many Core Systems
Yiming Zhao (South China University of Technology, P.R. China); Xiaohang Wang (SCUT, P.R. China); Yingtao Jiang and Mei Yang (University of Nevada, Las Vegas, USA); Amit Singh (University of Essex, United Kingdom (Great Britain)); Terrence Mak (University of Southampton, United Kingdom (Great Britain))
10:55 Holistic Energy Management with µProcessor Co-Optimization in Fully Integrated Battery-less IoTs
Josiah Hester, Jie Gu and Tianyu Jia (Northwestern University, USA)
11:20 Cloud Motion Vector Estimation Using Scalable Wireless Sensor Networks
Michael Gacusan and Venkatesan Muthukumar (University of Nevada Las Vegas, USA)
11:45 A Discontinuous Charging Technique with Programmable Duty-Cycle for Switched-Capacitor Based Energy Harvesting Circuits in IoT Applications
Sanad Kawar and Shoba Krishnan (Santa Clara University, USA); Khaldoon Abugharbieh (Princess Sumaya University for Technology, Jordan)

W1B: RF Circuits

Room: Salon F
Chair: Andrew Marshall (University of Texas at Dallas, USA)
10:30 An FSK Transceiver for USB Power Delivery in 0.14-Um CMOS Technology
Siamak Delshadpour (NXP Semiconductors, USA)
10:55 A 64 dB Dynamic Range Programmable Gain Amplifier for Dual Band WLAN 802.11Abg IF Receiver in 0.18 Um CMOS Technology
Siamak Delshadpour (NXP Semiconductors, USA)
11:20 Design and Analysis of 66GHz Voltage Controlled Oscillators for FMCW Radar Applications with Phase Noise Impact Consideration
Mehdi Nasrollahpour (San Jose State University, USA); Amir Mahdavi (Tabriz University, Iran); Sotoudeh Hamedi-Hagh (San Jose State University, USA)

Wednesday, September 5 12:10 - 13:30

Lunch

Wednesday, September 5 13:30 - 14:20

Wednesday PlenaryDetails

In-Memory Computing: The Resurgence
Vijaykrishnan Narayanan, Distinguished Professor of Computer Science & Engineering and Electrical Engineering, Pennsylvania State University, USA
Rooms: Salon D, Salon E
Chair: Ramalingam Sridhar (University at Buffalo, USA)

Compute-in-Memory (CiM) techniques focus on reducing data movement by integrating compute elements within or near the memory primitives. While there have been decades of research on various aspects of such logic and memory integration, the confluence of new technology changes and emerging workloads makes us revisit this design space. This talk focuses on new functionality embedded with SRAMs using emerging monolithic 3D integration. Properties of the new technology transform the costs of embedding such new functionality compared to prior efforts. This work also explores how compute functionality can be embedded into cross-point style non-volatile memory systems. The talk will provide insights into the benefits provided by the proposed technique and evaluate the energy efficiency of the proposed designs.

Wednesday, September 5 14:20 - 14:40

Break

Wednesday, September 5 14:40 - 16:20

W2A: Emerging and Evolutionary Design

Rooms: Salon D, Salon E
Chair: Danella Zhao (Old Dominion University, USA)
14:40 A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems
Md Musabbir Adnan and Sagarvarma Sayyaparaju (University of Tennessee Knoxville, USA); Catherine Schuman (Oak Ridge National Laboratory, USA); Bon Woong Ku and Sung Kyu Lim (Georgia Institute of Technology, USA); Garrett Rose (University of Tennessee, USA)
15:05 A Low-Power Arithmetic Element for Multi-Base Logarithmic Computation on Deep Neural Networks
Jiawei Xu and Yuxiang Huan (Fudan University, P.R. China); Zhuo Zou (Fudan University & KTH Royal Institute of Technology, Sweden); Lirong Zheng (Fudan University, P.R. China)
15:30 A Scalable High-Precision and High-Throughput Architecture for Emulation of Quantum Algorithms
Naveed Mahmud and Esam El-Araby (University of Kansas, USA)
15:55 Taxonomy of Spatial Parallelism on FPGAs for Massively Parallel Applications
Arnab Ardhendu Purkayastha, Suhas Ashok Shiddibhavi and Hamed Tabkhi (University of North Carolina at Charlotte, USA)

W2B: High Performance Low Power Circuits

Room: Salon F
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)
14:40 An Output-Capacitorless Adaptively Biased Low-Dropout Regulator with Maximum 132-MHz UGF and Without Minimum Loading Requirement
Siji Huang, Yicheng Li, Bing Mo and Jianping Guo (Sun Yat-sen University, P.R. China); DiHu Chen (Sun Yat-Sen University, P.R. China)
15:05 An Ultra-Low-Voltage Sub-threshold Pseudo-Differential CMOS Schmitt Trigger
Yasin Bastan (Shahid Rajaee Teacher Training University, Iran); Ali Nejati and Sara Radfar (Shahid Rajaee Teacher Training University); Parviz Amiri (Shahid Rajaee Teacher Training univ., Iran); Mehdi Nasrollahpour and Sotoudeh Hamedi-Hagh (San Jose State University, USA)
15:30 Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching
Keyvan Ramezanpour (VIRGINIA TECH, USA); Paul Ampadu (Virginia Tech, USA)
15:55 A New Circuit Topology for High-Performance Pulsed Time-of-Flight Laser Radar Receivers
Kaiyou Li, Haoxin Zheng, Jianping Guo and Bing Mo (Sun Yat-sen University, P.R. China); DiHu Chen (Sun Yat-Sen University, P.R. China)

Wednesday, September 5 16:20 - 18:00

W3A: Security

Rooms: Salon D, Salon E
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)
16:20 Policy-Based Security Modelling and Enforcement Approach for Emerging Embedded Architectures
Matthew Hagan (Queens University Belfast, United Kingdom (Great Britain)); Fahad Manzoor Siddiqui (Queens University Belfast & The Centre for Secure Information Technologies (CSIT), United Kingdom (Great Britain)); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))
16:45 An Entropy Analysis Based Intrusion Detection System for Controller Area Network in Vehicles
Qian Wang (University of Maryland, USA); Zhaojun Lu (Huazhong University of Science and Technology, P.R. China); Gang Qu (University of Maryland, USA)
17:10 A High-performance VLSI Architecture of the PRESENT Cipher and Its Implementations for SoCs
Jai Gopal Pandey (CSIR-Central Electronics Engineering Research Institute, Pilani, India); Tarun Goel (Central Research Laboratory (CRL), India); Mausam Nayak and Chhavi Mitharwal (Banasthali Vidyapith, India); Abhijit Karmakar and Raj Singh (CSIR-CEERI, Pilani, Rajasthan, India)
17:35 Leakage Power Analysis (LPA) Attack in Breakdown Mode and Countermeasure
Weize Yu and Yiming Wen (Old Dominion University, USA)

W3B: Reconfigurable Architectures and Applications

Room: Salon F
Chairs: Paul Ampadu (Virginia Tech, USA), James E Stine (Oklahoma State University, USA)
16:20 Optimized Counter-Based Multi-Ported Memory Architectures for Next-Generation FPGAs
Darshika G Perera (University of Colorado at Colorado Springs, USA & University of Victoria, Canada); S. Navid Shahrouzi (University of Colorado at Colorado Springs, USA)
16:45 Performance Modeling of VIA-switch FPGA for Device-Circuit-Architecture Co-Optimization
Tatsuhiro Higuchi, Tohru Ishihara and Hidetoshi Onodera (Kyoto University, Japan)
17:10 A Content-Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique
Tanja Harbaum, Matthias Balzer, Juergen Becker and Marc Weber (Karlsruhe Institute of Technology, Germany)
17:35 An ASIC Design of Multi-Electrode Digital Basket Catheter Systems with Reconfigurable Compressed Sampling
Haoming Chu, Yuxiang Huan and Dongxuan Bao (Fudan University, P.R. China); Bengt Kallback (Cathprint AB, Sweden); Yajie Qin (Royal Institute of Technology, Sweden); Zhuo Zou (Fudan University & KTH Royal Institute of Technology, Sweden); Lirong Zheng (Fudan University, P.R. China)

Wednesday, September 5 18:00 - 20:00

WP: Poster Session & Reception

Room: Salon F
Chair: Mircea Stan (University of Virginia, USA)
A Multi-Objective Architecture Optimization Method for Application-Specific NoC Design
Changqing Xu (School of Microelectronics, Xidian University, P.R. China); Yi Liu (School of Microelectronics, Xidian University); Yintang Yang (Xidian University, P.R. China)
Building an Acceleration Overlay for Novice Students
Shrikant S Jadhav (North Carolina A&T State University, USA); Noah LaMoyne and Alan Chen (San Jose State University, USA); Clay Gloster (NC A & T University, USA); Dylan Yang (Crescenta Valley High School, USA); Sunmin Yun and Youngsoo Kim (San Jose State University, USA)
Pro-Active Policing and Policy Enforcement Architecture for Securing MPSoCs
Fahad Manzoor Siddiqui (Queens University Belfast & The Centre for Secure Information Technologies (CSIT), United Kingdom (Great Britain)); Matthew Hagan (Queens University Belfast, United Kingdom (Great Britain)); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))
Compact Modeling and Design of Magneto-electric Transistor Devices and Circuits
Nishtha Sharma (University of Texas at Dallas, USA); Christian Binek (University of Nebraska, USA); Andrew Marshall (University of Texas at Dallas, USA); Jonathan Bird (The State University of New York, USA); Peter Dowben (University of Nebraska-Lincoln, USA); Dmitri Nikonov (Intel Corporation, USA)
Flexible Self-Healing Router for Reliable and High-Performance Network-on-Chips Architecture
Kasem Khalil, Omar Eldash, Ashok Kumar and Magdy Bayoumi (University of Louisiana at Lafayette, USA)
Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis
Mattia Cacciotti (École Polytechnique Fédérale de Lausanne, Switzerland); Vincent Camus (ICLAB, EPFL, Switzerland); Jeremy Schlachter, Alessandro Pezzotta and Christian Enz (Ecole Polytechnique Federale de Lausanne, Switzerland)
PAT-NOXIM: A Precise Power & Thermal Cycle-Accurate NoC Simulator
Hakem Beitollahi, Amin Norollah and Danesh Derafshi (Iran University of Science and Technology, Iran); Ahmad Patooghy (University of Central Arkansas, USA)
PCNNA: A Photonic Convolutional Neural Network Accelerator
Armin Mehrabian, Yousra Alkabani, Volker Sorger and Tarek El-Ghazawi (The George Washington University, USA)
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks
Steffen Baehr, Fabian Kempf and Juergen Becker (Karlsruhe Institute of Technology, Germany)
Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits
Lafifa Jamal and Riaz Uddin (University of Dhaka, Bangladesh)
Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms
Peter A Zientara (The Pennsylvania State University, USA); Vijaykrishnan Narayanan and Jack Sampson (Pennsylvania State University, USA)
An Automated Fault Injection Platform for Fault Tolerant FFT Implemented in SRAM-Based FPGA
ChuangAn Mao (Beijing Institute Of Technology, P.R. China); Yu Xie, He Chen and Yizhuang Xie (Beijing Institute of Technology, P.R. China); Hao Shi (Tsinghua University, USA)
A Quantitative Approach to SoC Functional Safety Analysis
Shivakumar Chonnad (Synopsys Inc, USA); Vladimir Litovtchenko (Synopsys GmbH, Germany); Radu Iacob (Synopsys Inc, USA)
A 81nW Error Amplifier Design for Ultra Low Leakage Retention Mode Operation of 4Mb SRAM Array in 40Nm LSTP Technology
Ankush Mamgain (Indraprastha Institute of Information Technology, India); Anuj Grover (ST Microelectronics, India)
A Practical Sense Amplifier Design for Memristive Crossbar Circuits (PUF)
Mesbah Uddin (The University of Tennessee, USA); Garrett Rose (University of Tennessee, USA)

Thursday, September 6

Thursday, September 6 9:00 - 9:50

Thursday Keynote

New Paradigms for Energy-Efficient Computing Beyond the Moore's Law Era
Tarek El-Ghazawi, Professor and IEEE Fellow, The George Washington University, USA
Rooms: Salon D, Salon E
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

Due to the end of the Moore's law in clocking and Dennard's scaling, we are reaching very crippling limits with our current von Neumann processor paradigms. All the help is sought from both technology and architectures to innovate and engender new processing paradigms that can overcome those limitations and define the future of computing. New ideas and directions ranged from neuromorphic processors, to analog, memristors, quantum and the use of nano photonics. This talk will examine a number of these emerging directions and work by the community including ours and evaluate some of the associated implications for the future of computing.

Tarek El-Ghazawi is a Professor in the Department of Electrical and Computer Engineering Opens in a new window at The George Washington University Opens in a new window, where he leads the university-wide Strategic Academic Program in High-Performance Computing Opens in a new window. He is the founding director of The GW Institute for Massively Parallel Applications and Computing Technologies (IMPACT) Opens in a new window and a founding Co-Director of the NSF Industry/University Center for High-Performance Reconfigurable Computing (CHREC) Opens in a new window. El-Ghazawi's research interests include high-performance computing, computer architectures, reconfigurable, embedded computing and computer vision. He is one of the principal co-authors of the UPC parallel programming language and the first author of the UPC book from John Wiley and Sons. He has received his Ph.D. degree in Electrical and Computer Engineering from New Mexico State University in 1988. El-Ghazawi has published close to 250 refereed research publications in this area.

Thursday, September 6 9:50 - 10:40

Thursday Morning PlenaryDetails

Neural Networks on Chip: From CMOS Accelerators to In-Memory-Computing
Yu Wang, Associate Professor, E.E. Dept., Tsinghua University, Beijing, China
Rooms: Salon D, Salon E
Chair: Hai (Helen) Li (Duke University, USA)

Artificial neural networks, which dominate artificial intelligence applications such as object recognition and speech recognition, are in evolution. To apply neural networks to wider applications, customized hardware are necessary since CPU and GPU are not efficient enough. Numerous architectures are proposed in the past 4 years to boost the energy efficiency of deep learning inference processing, including Tsinghua and Deephi's effort. In this talk, we will talk about different architectures based on CMOS technologies, including 200GOPS/W FPGA accelerators, about 1-5TOPS/W chips with DDR subsystems, and over 50TOPs/W chips with everything on chip. The possibilities and trends of adopting emerging NVM technology for efficient learning systems, i.e., in-memory-computing, will also be discussed as one of the most promising ways to improve the energy efficiency.

Yu Wang received his B.S. degree in 2002 and Ph.D. degree (with honor) in 2007 from Tsinghua University, Beijing. He is currently a Tenured Associate Professor with the Department of Electronic Engineering, Tsinghua University. His research interests include brain inspired computing, application specific hardware computing, parallel circuit analysis, and power/reliability aware system design methodology. Dr. Wang has authored and coauthored over 200 papers in refereed journals and conferences. He has received Best Paper Award in FPGA 2017, NVMSA17, ISVLSI 2012, and Best Poster Award in HEART 2012 with 9 Best Paper Nominations. He is a recipient of DAC Under-40 Innovator Award in 2018 and IBM X10 Faculty Award in 2010. He served as TPC chair for ISVLSI 2018, ICFPT 2011 and Finance Chair of ISLPED 2012-2016, and served as program committee member for leading conferences in these areas, including top EDA conferences such as DAC, DATE, ICCAD, ASP-DAC, and top FPGA conferences such as FPGA and FPT. Currently he serves as Co-EIC for SIGDA E-Newsletter, Associate Editor for IEEE Trans on CAS for Video Technology, IEEE Transactions on CAD, and Journal of Circuits, Systems, and Computers. He also serves as guest editor for Integration, the VLSI Journal and IEEE Transactions on Multi-Scale Computing Systems. He is a recipient of NSF China Excellent Young Scholar, and is now serving as ACM distinguished speaker. He is an IEEE/ACM senior member. He is the co-founder of Deephi Tech (valued over 150M USD), which is a leading deep learning processing platform provider.

Thursday, September 6 10:40 - 11:00

Break

Thursday, September 6 11:00 - 12:15

T1A: Memory Circuits and Applications

Rooms: Salon D, Salon E
Chair: Mircea Stan (University of Virginia, USA)
11:00 Reducing Memory Interference Latency of Safety-Critical Applications via Memory Request Throttling and Linux Cgroup
Jungho Kim, Daesik Ham, Soonhyun Noh, Philkyue Shin and Seongsoo Hong (Seoul National University, Korea)
11:25 Memory Access Driven Memory Layout and Block Replacement Techniques for Compressed Deep Neural Networks
Byungmin Ahn and Taewhan Kim (Seoul National University, Korea)
11:50 A Learning-guided Hierarchical Approach for Biomedical Image Segmentation
Huaipan Jiang, Anup Sarma and Jihyun Ryoo (Pennsylvania State University, USA); Jagadish B. Kotra (AMD Research, USA); Meena Arunachalam (Intel, USA); Chita R. Das (The Pennsylvania State University, USA); Mahmut Taylan Kandemir (Penn State University, USA)

T1B: Digital and Mixed-Signal Circuits

Room: Salon F
Chair: Andrew Marshall (University of Texas at Dallas, USA)
11:00 Designing Algorithm for the High Speed TIQ ADC, with Improved Accuracy
Jun Hyuk Park and Soobum Kwon (Mtec Global Co., Ltd., USA); Kyusun Choi (Penn State University, USA)
11:25 Universal CMOS Diamond-graph Circuit for Embedded Computing
Shun-Wen Cheng (National Chip Implementation Center, National Applied Research Laboratories, Taiwan); Chun-Pin Lin and Chi-Shi Chen (National Chip Implementation Center, Taiwan); Wei-Chang Tsai (National Chip Implementation Center, NARL, Taiwan)
11:50 MPT: Multiple Parallel Tempering for High-Throughput MCMC Samplers
Morteza Hosseini (University of Maryland, Baltimore County, USA); Rashidul Islam (UMBC, USA); Lahir Marni (University of Maryland, Baltimore County, USA); Tinoosh Mohsenin (University of Maryland Baltimore County, USA)

Thursday, September 6 12:15 - 13:30

Lunch

Thursday, September 6 13:30 - 14:20

Thursday Afternoon PlenaryDetails

Predictive Analytics for Anomaly Detection and Failure Prediction in Complex Core Routers
Krishnendu Chakrabarty, Distinguished Professor and Chair of Electrical and Computer Engineering, Duke University, USA
Rooms: Salon D, Salon E
Chair: Hai (Helen) Li (Duke University, USA)

Prognostic diagnosis is desirable for commercial core router systems to ensure early failure prediction and fast error recovery. The effectiveness of prognostic diagnosis depends on whether anomalies can be accurately detected before a failure occurs. However, traditional anomaly detection techniques fail to detect "outliers" when the statistical properties of the monitored data change significantly with time. This talk will describe recent advances in using time-series data analysis to detect anomalies through the real-time monitoring of key performance indicators in core routers. The speaker will describe the design of a changepoint-based anomaly detector ad health-status analyzer that first detects changepoints from collected time-series data, and then utilizes these changepoints to detect anomalies. A clustering method is first used to identify a wide range of normal/abnormal patterns from changepoint windows. Symbolic aggregation approximation and moving-average-based trend approximation are utilized to encode complex time series. Hierarchical agglomerative clustering and sequitur rule discovery are then to learn important global and local patterns. A comprehensive set of experimental results will be presented for data collected during 30 days of field operation from over 20 core routers deployed by customers of a major telecom company.

Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor and Department Chair of Electrical and Computer Engineering, and Professor of Computer Science, at Duke University. He is also a Hans Fischer Senior Fellow at the Institute for Advanced Study, Technical University of Munich, Germany.

Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Award from the Alexander von Humboldt Foundation, Germany, the IEEE Transactions on CAD Donald O. Pederson Best Paper Award (2015), the ACM Transactions on Design Automation of Electronic Systems Best Paper Award (2017), and over a dozen best paper awards at major conferences. He is also a recipient of the IEEE Computer Society Technical Achievement Award (2015), the IEEE Circuits and Systems Society Charles A. Desoer Technical Achievement Award (2017), and then Semiconductor Research Corporation Technical Excellence Award (2018). He is a recipient of the Japan Society for the Promotion of Science (JSPS) Fellowship in the "Short Term S-Nobel Prize level" category.

Prof. Chakrabarty's current research projects include: testing and design-for-testability of integrated circuits and systems; microfluidic biochips and cyberphysical systems; data analytics for fault diagnosis, failure prediction, anomaly detection, and hardware security; neuromorphic computing systems. He is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He is a recipient of the 2008 Duke University Graduate School Dean's Award for excellence in mentoring, and the 2010 Capers and Marion McDonald Award for Excellence in Mentoring and Advising, Pratt School of Engineering, Duke University. He has served as a Distinguished Visitor of the IEEE Computer Society (2005-2007, 2010-2012), a Distinguished Lecturer of the IEEE Circuits and Systems Society (2006-2007, 2012-2013), and an ACM Distinguished Speaker (2008-2016).

Prof. Chakrabarty served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012 and ACM Journal on Emerging Technologies in Computing Systems during 2010-2015. Currently he serves as the Editor-in-Chief of IEEE Transactions on VLSI Systems.

Thursday, September 6 14:20 - 14:40

Break

Thursday, September 6 14:40 - 16:45

T2A: Special Session: ML/AI in Startups and Government Agencies

Ren Wu, Novumind CEO, Chris Nicol, Wave Computing CTO, Jeremy Holleman, Syntiant CTO, Tom St John, Wave Computing Chief Scientist and Director, Hava Siegelmann, DARPA, Sankar Basu, NSF
Rooms: Salon D, Salon E
Chair: Mircea Stan (University of Virginia, USA)

Deep Learning Architectures: An Industry and Government Agencies Perspective

The trend of migrating deep learning from the data center to the edge of the network is driving the need for specialized, low-power machine learning SoCs. These systems are being deployed in applications that require enhanced AI capabilities like ADAS systems in vehicles, home and industrial robotics and all manner of consumer electronics. Indeed, there is unlikely to be a single application or industry vertical that does not have an AI roadmap of some kind. This trend is disrupting the maturing semiconductor industry that was, until recently, suffering from a severe lack of investment for innovation. Within a few years, a multitude of new and innovative architectures for deep learning acceleration have appeared on the market. This session provides an overview of some of the work in semiconductor startup companies as well as an introduction to the MLPerf benchmarking activity that aims to assist with the AI hardware procurement process. The representatives from NSF and DARPA will go over some of the exciting new initiatives and programs coming from government in support of ML/AI activities.

During this special session, machine learning experts from Wave Computing, Syntiant, Novumind, DARPA and NSF will discuss these AI acceleration challenges, as well as their solutions and architecture implementations.

T2B: Design Track

Room: Salon F
Chairs: Andrew Marshall (University of Texas at Dallas, USA), James E Stine (Oklahoma State University, USA)
14:40 DFT, PD & PO Aspects of Xavier - Flagship SOC for Autonomous Driving and Deep Learning
15:05 Integrated Surround & CMS Automotive SoC
Mihir N Mody (Texas Instruments, India); Kedar Chitnis, Piyali Goswami, Brijesh Jadav and Shiju Sivasankaran (Texas Instruments India Pvt. Ltd., India); Gregory Shurtz (Texas Instruments, USA); Rajat Sagar (Texas Instrumnets, India); Shashank Dabral (Texas Instruments Inc., USA); Prasad Jondhale (Texas Instruments India Pvt. Ltd., India); Yashwant Dutt (Texas Instruments, India); Jason Jones (Texas Instruments, USA)
15:30 10T Differential-Signal SRAM Design in a 14-Nm FinFET Technology for High-Speed Application
15:55 Smart Silicon Substrate for Quick Time to Market Chip-Stacks and Systems-in-Package
16:20 Low Power 20 Gbps Type-C USB3.2/DP1.4/Thunderbolt3 Combo Linear Redriver in 0.25 Μm BiCMOS Technology
Siamak Delshadpour (NXP Semiconductors, USA)

Thursday, September 6 16:45 - 18:00

Panel Discussion: ML/AI in Startups and Government Agencies

Ren Wu, Novumind CEO, Chris Nicol, Wave Computing CTO, Jeremy Holleman, Syntiant CTO, Tom St John, Wave Computing Chief Scientist and Director, Hava Siegelmann, DARPA, Sankar Basu, NSF, Yu Wang, DeePhi co-founder
Rooms: Salon D, Salon E
Chair: Mircea Stan (University of Virginia, USA)

Deep Learning Architectures: An Industry and Government Agencies Perspective

The trend of migrating deep learning from the data center to the edge of the network is driving the need for specialized, low-power machine learning SoCs. These systems are being deployed in applications that require enhanced AI capabilities like ADAS systems in vehicles, home and industrial robotics and all manner of consumer electronics. Indeed, there is unlikely to be a single application or industry vertical that does not have an AI roadmap of some kind. This trend is disrupting the maturing semiconductor industry that was, until recently, suffering from a severe lack of investment for innovation. Within a few years, a multitude of new and innovative architectures for deep learning acceleration have appeared on the market. This panel will answer questions about some of the work in semiconductor startup companies as well as an introduction to the MLPerf benchmarking activity that aims to assist with the AI hardware procurement process. The representatives from NSF and DARPA will go over some of the exciting new initiatives and programs coming from government in support of ML/AI activities.

During this panel, machine learning experts from Wave Computing, Syntiant, Novumind, DeePhi, DARPA and NSF will answer questions about these AI acceleration challenges, as well as their solutions and architecture implementations.

Thursday, September 6 18:30 - 21:00

Banquet with Banquet Speech

"The Good, the Bed and the Ugly": An ambitious suicide mission to commercialise academic research via a technology start-up
Sakir Sezer, Queen's University, Belfast
Chair: Ramalingam Sridhar (University at Buffalo, USA)

Titan IC, is a University start-up company, established with the mission to commercialise academic research in high-performance content processing. In this talk Prof Sezer will introduce Titan IC and the underpinning technologies based on academic research, targeted technology markets and business engagements with top Silicon Valley companies. The second part of the talk will address challenges faced by the founders in establishing a high-tech start-up dealing with productization of IP, raising funding, developing a successful business model, operations, marketing and customer engagements. The final part of the talk will address "lessons learned" with recommendations for academics and researchers considering a similar technology start-up.

Friday, September 7

Friday, September 7 9:00 - 10:15

F1A: MPSoC and Design Methodologies I

Rooms: Salon D, Salon E
Chair: Mircea Stan (University of Virginia, USA)
9:00 Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications
Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen and Chien-Tung Liu (National Chung-Cheng University, Taiwan); Tay-Jyi Lin (National Chung Cheng University, Taiwan); Jinn-Shyan Wang (National Chung Cheng University, Taiwan)
9:25 Co-optimizing CPUs and Accelerators in Constrained Systems
Alec Roelke and Mircea Stan (University of Virginia, USA)
9:50 Power-Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era
Md Farhadur Reza (George Washington University, USA); Magdy Bayoumi (University of Louisiana at Lafayette, USA); Danella Zhao (Old Dominion University, USA)

F1B: Low Power Circuits I

Room: Salon F
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)
9:00 A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications
Samira Ataei and James E Stine (Oklahoma State University, USA)
9:25 0.4V Reconfigurable Near-Threshold TCAM in 28Nm High-k Metal-Gate CMOS Process
Yun-Sheng Chan and Po-Tsang Huang (National Chiao Tung University, Taiwan); Shang-Lin Wu (Nation Chiao Tung University, Taiwan); Sheng-Chi Lung and Wei-Chang Wang (Faraday Technology Corporation, Taiwan); Wei Hwang and Ching-Te Chuang (National Chiao Tung University, Taiwan)
9:50 Energy-Efficient SRAM Design with Data-Aware Dual-Modes 10T Storage Cell for CNN Processors
Han Xu and Fei Qiao (Tsinghua University, P.R. China); Zhe Chen (Beijing Jiaotong University, P.R. China); Qi Wei (Tsinghua University, P.R. China); Li Luo (Beijing Jiaotong University, P.R. China); Xinjun Liu and Huazhong Yang (Tsinghua University, P.R. China)

Friday, September 7 10:15 - 10:35

Break

Friday, September 7 10:35 - 11:50

F2A: MPSoC and Design Methodologies II

Rooms: Salon D, Salon E
Chair: Danella Zhao (Old Dominion University, USA)
10:35 A One-to-many Traffic Aware Wireless Network-in-Package for Multi-Chip Computing Platforms
Meraj Ahmed, Amlan Ganguly, Sajeed Shahriat, Hardeep Purswani and Naseef Mansoor (Rochester Institute of Technology, USA)
11:00 Centralized Priority Management Allocation for Network-on-Chip Router
Pengzhan Yan and Ramalingam Sridhar (University at Buffalo, USA)
11:25 Broadcast- And Power-aware Wireless NoC for Barrier Synchronization in Parallel Computing
Hemanta Kumar Mondal (University of Southern Brittany (UBS)Lab-STICC Lorient France, India); Rodrigo Cadore Cataldo (University of Southern Brittany (UBS) Lab-STICC Lorient France, France); César Marcon (PUCRS - Pontifícia Universidade Católica do Rio Grande do Sul, Brazil); Kevin Martin (University of Bretagne-Sud & Lab-STICC, France); Sujay Deb (IIIT Delhi, India); Jean-Philippe Diguet (Lab-STICC UBS, France)

F2B: Low Power Circuits II

Room: Salon F
Chair: Mircea Stan (University of Virginia, USA)
10:35 A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs
Chien-Tung Liu, Zhe-Wei Chang and Shih-Nung Wei (National Chung-Cheng University, Taiwan); Jinn-Shyan Wang (National Chung Cheng University, Taiwan); Tay-Jyi Lin (National Chung Cheng University, Taiwan)
11:00 A 32kHz Crystal Oscillator Leveraging Voltage Scaling in an Ultra-Low Power 40nA Real-Time Clock
Mathieu Coustans and François Krummenacher (EPFL, Switzerland); Luca Rossi, Yves Godat, Mario Dellea and Yves Sierro (EM Microelectronic, Switzerland); Silvio DallaPiazza (Microcrystal, Switzerland); Maher Kayal (Swiss Federal Institute of Technology, Lausanne, Switzerland)
11:25 0.5V 10MS/s 9-Bits Asynchronous SAR ADC for BLE Receivers in 180Nm CMOS Technology
Hugo Hernandez (Federal University of Mato Grosso, Brazil); Lucas Severo (Universidade Federal do Pampa, Brazil); Wilhelmus Van Noije (University of São Paulo, São Paulo, Brazil)

Friday, September 7 11:50 - 12:00

Closing Remarks

Helen Li, Conference Chair, Mircea Stan, TPC chair
Rooms: Salon D, Salon E