Cyber-physical systems are engineered systems that require tight conjoining of and coordination between the computational (discrete) and the physical (continuous). Cyber-physical systems are rapidly penetrating every aspect of our lives, with potential impact on sectors critical to national security and competitiveness, including aerospace, automotive, chemical production, civil infrastructure, energy, finance, healthcare, manufacturing, materials, and transportation. As these systems fulfill the promise of the Internet of Things, smart cities, household robots, and personalized medicine, we need to ensure they are trustworthy: reliable, secure, and privacy-preserving. This talk will look at cyber-physical systems from the lens of trustworthy computing. Throughout my talk, I will raise research challenges for how to make cyber-physical systems trustworthy.

Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Applications include manufacturing, transportation, energy production and distribution, biomedical, smart buildings, and military systems, to name a few. Increasingly, today, such systems leverage Internet technology, despite a significant mismatch in technical objectives. A major challenge today is to make this technology reliable, predictable, and controllable enough for "important" things, such as safety-critical and mission-critical systems. In this talk, I will analyze how emerging technologies can translate into better models and better engineering methods for this evolving Internet of important things. I will particularly focus on embedded processor design that can significantly improve determinism and reduce power consumption for embedded software.

14:00 - 14:05: Opening by Chair
14:05 - 14:20: IoT: From Vision to Reality (Magdy Bayoumi, University of Louisiana at Lafayette)
14:20 - 14:50: IoT: Design Challenges and Opportunities (Danielle Griffith, TI)
14:50 - 15:35: IoT: No more Moore? Let's break the law! (Wolf Richter, President, EPIC Semiconductor)

16:00 - 16:30: Machine Learning Accelerators for IoTs (Ram Krishnamurthy, Intel Corp)
16:30 - 17:00: IoT System Level Challenges and Applications (Ramalingam Sridhar, SUNY at Buffalo)
17:00 - 17:30: Interactive session with all the speakers
17:30 - 17:40: Closing by Chair

Rumors of Moore's Law demise have been greatly exaggerated! While transistors are not getting simultaneously smaller, faster and lower power every couple of years like for the past several decades, inexorable forces to cram more devices together are still running strong, except that they are now pushing upwards in the third dimension. Heterogeneity, monolithic vs. TSV-based scaling for 3D, and closing the energy loop (cooling and power delivery) will punctuate this talk as it explores the challenges and opportunities that IoT systems of the future face as they move away from planar Systems-on-Chip (SoC) to becoming three dimensional Systems-on-Anything (SoX, e.g. Systems-on-Package, Systems-on-Interposer, etc.)

This talk presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as encryption, graphics and media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra mobile SoCs, dynamic on-the fly configurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

10:45 - 10:50: Opening by Chair
10:50 - 11:15: Introduction (Sakir Sezer, Queen's University Belfast & CTO Titan IC, United Kingdom)
11:15 - 12:00: SoC Challenges Enabling Server-based Networking (Ron Swartzentruber, Senior Principal Engineer, Netronome)

13:30 - 14:15: Safe Planning and Control Under Uncertainty (Ashish Kapoor, Senior Researcher, Microsoft Research)
14:15 - 15:00: In Silicon We Trust - How to Fix the Internet of Broken Things (Cesare Garlati, Chief Security Strategist, prpl Foundation)
15:00 - 15:10: Interactive session with all the speakers
15:10: Closing by chair

PANELISTS:
Ron Swartzentruber (Senior Principal Engineer, Netronome)
Lubna Dajani (Chief Strategy Officer, Intercede)
Ram Krishnamurthy (Senior Principal Engineer, Intel)
Mircea Stan (Professor, University of Virginia)
Yong Lian (Professor, York University)

This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and performance optimization features that keep the development time short and productivity high.

This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and performance optimization features that keep the development time short and productivity high.

Enjoy the wonder of flight in one of Seattle's most spectacular settings. Walk the aisle of JFK's Air Force One and climb aboard the West Coast's only Concorde. Revel in the history and heroics of WWI and WWII. Barrel-roll a Mustang, land on the moon, and soar over Puget Sound in a simulator. Experience the excitement of the space race and sit at the controls of the world's fastest jet. From the Wright brothers to the exploration of Mars, you'll find it at The Museum of Flight!

This 15-acre campus includes over 160 air and spacecraft, the original Boeing Aircraft factory, flight simulators, and dozens of fun, interactive exhibits and family activities. From the world's oldest fighter plane to the supersonic Concorde, the only full-scale NASA Space Shuttle Trainer and the beautiful Boeing 787 Dreamliner, you'll see the machines and experience the stories of those who flew them. The unique, 3-acre Aviation Pavillion offers the dramatic development of large aircraft in an open-air gallery with a cafe and children's playground.

This tour is not included in your conference registration. Ticket Price: $37 + tax/ticketing fee, includes transportation and admission to the museum.