Program for 2016 29th IEEE International System-on-Chip Conference (SOCC)

Time Courtyard Ballroom Courtyard Foyer East Federal Municipal North Superior Visions (28th Floor) Vista

Tuesday, September 6

08:00-09:00 Breakfast
09:00-10:30     Tutorial 1A: Design Challenges for the Internet of Things     Tutorial 1B: Transistors: Past, Present and Future      
10:30-10:45 Coffee Break
10:45-12:15     Tutorial 2A: 3D Integration - Challenges and Advantages     Tutorial 2B: CMOS Integrated System on a Chip for Neural Interface Applications      
12:15-14:00 Lunch
14:00-15:30     Tutorial 3A: Bringing Cores Closer Together: The Wireless Revolution in On-Chip Communication     Tutorial 3B: The Design Challenges for Self-Powered Wireless Wearable ECG Sensor SoC      
15:30-15:45 Coffee Break
15:45-17:15     Tutorial 4A: Supply Voltage Noise and Mitigation for Real World SoCs     Tutorial 4B: ADC Design - From System Architecture to Transistor Level Design      

Wednesday, September 7

07:30-08:30 Breakfast
08:30-08:45 Opening Remarks                
08:45-09:00 Technical Program Overview                
09:00-10:00 Opening Keynote                
10:00-10:15 Coffee Break
10:15-11:15 Plenary I                
11:20-12:35       RF, Analog Design I Best Paper Award I   Design Track    
12:35-14:00 Lunch
14:00-15:40       SoC Design Methods and Algorithms I Industry Forum: IoT for Real Life Part I   Special Session: Emerging Trends in SoC Testing    
15:40-16:00 Coffee Break
16:00-17:40       Emerging and Evolutionary Design Algorithms Industry Forum: IoT for Real Life Part II   Application Specific SoC Designs    
18:00-19:30   Poster Session & Reception              

Thursday, September 8

07:30-08:30 Breakfast
08:30-09:30 Keynote II                
09:30-10:30 Plenary II                
10:30-10:45 Coffee Break
10:45-12:00       Special Session: SoC Architectures for Machine Learning through Inexactness Industry Forum: Data Analytics and Security in IoT Part I   Best Paper Award II    
12:00-13:30 Lunch
13:30-15:10       Advanced SoC Components Industry Forum: Data Analytics and Security in IoT Part II   RF, Analog Design II    
15:10-15:30 Coffee Break
15:30-17:00 Panel Discussion: Spreading intelligence across a trillion devices and making the most of it - How pervasive will sensemaking be in IoT, and which applications will take advantage of it?                
17:30-18:30                 Cocktail Reception
18:30-21:00               Conference Banquet  

Friday, September 9

07:30-08:30 Breakfast
08:30-10:10       SoC Design Methods and Algorithms II Intel Training Workshop Part I   Special Session: Emerging Stochastic Computing and Neuromorphic Computing: Arithmetic, Algorithm, and Applications    
10:10-10:30 Coffee Break
10:30-12:10       Low Power Design Intel Training Workshop Part II   Special Session: Security and Validation in Mobile, Embedded, and IoT Systems    
12:10-13:00 Lunch
13:00-17:30 Post Conference Event: The Museum of Flight Tour (not included in registration)

Tuesday, September 6

Tuesday, September 6, 08:00 - 09:00

Breakfast

Tuesday, September 6, 09:00 - 10:30

Tutorial 1A: Design Challenges for the Internet of Things

Danielle Griffith, Texas Instruments, Inc., USA
Room: East
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)

Tutorial 1B: Transistors: Past, Present and Future

Gururaj Shamanna, Qualcomm India Pvt Limited, India
Room: North
Chair: Sao-Jie Chen (National Taiwan University, Taiwan)

Tuesday, September 6, 10:30 - 10:45

Coffee Break

Tuesday, September 6, 10:45 - 12:15

Tutorial 2A: 3D Integration - Challenges and Advantages

Malgorzata Chrzanowska-Jeske, Portland State University, USA
Room: East
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

Tutorial 2B: CMOS Integrated System on a Chip for Neural Interface Applications

Jacques Christophe Rudell, University of Washington, USA
Room: North
Chair: Yu Huang (Mentor Graphics, USA)

Tuesday, September 6, 12:15 - 14:00

Lunch

Tuesday, September 6, 14:00 - 15:30

Tutorial 3A: Bringing Cores Closer Together: The Wireless Revolution in On-Chip Communication

Partha Pande, Washington State University, USA
Room: East
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)

Tutorial 3B: The Design Challenges for Self-Powered Wireless Wearable ECG Sensor SoC

Yong Lian, National University of Singapore, Singapore
Room: North
Chair: Andrew Marshall (University of Texas at Dallas, USA)

Tuesday, September 6, 15:30 - 15:45

Coffee Break

Tuesday, September 6, 15:45 - 17:15

Tutorial 4A: Supply Voltage Noise and Mitigation for Real World SoCs

Visvesh Sathe, University of Washington, USA
Room: East
Chair: Andrew Marshall (University of Texas at Dallas, USA)

Tutorial 4B: ADC Design - From System Architecture to Transistor Level Design

Bhibhudatta Sahoo University of Illinois, Urbana-Champaign, USA and Vishal Saxena, University of Idaho, USA
Room: North
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)

Wednesday, September 7

Wednesday, September 7, 07:30 - 08:30

Breakfast

Wednesday, September 7, 08:30 - 08:45

Opening Remarks

Danella Zhao, SOCC 2016 Conference Chair
Room: Courtyard Ballroom
Chair: Danella Zhao (Old Dominion University, USA)

Wednesday, September 7, 08:45 - 09:00

Technical Program Overview

Karan Bhatia, SOCC 2016 Technical Program Chair
Room: Courtyard Ballroom
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)

Wednesday, September 7, 09:00 - 10:00

Opening Keynote

Crashing Drones and Hijacked Cameras: CyberTrust Meets CyberPhysical
Jeannette M. Wing, Corporate Vice President, Microsoft Research, USA
Room: Courtyard Ballroom
Chair: Danella Zhao (Old Dominion University, USA)

Cyber-physical systems are engineered systems that require tight conjoining of and coordination between the computational (discrete) and the physical (continuous). Cyber-physical systems are rapidly penetrating every aspect of our lives, with potential impact on sectors critical to national security and competitiveness, including aerospace, automotive, chemical production, civil infrastructure, energy, finance, healthcare, manufacturing, materials, and transportation. As these systems fulfill the promise of the Internet of Things, smart cities, household robots, and personalized medicine, we need to ensure they are trustworthy: reliable, secure, and privacy-preserving. This talk will look at cyber-physical systems from the lens of trustworthy computing. Throughout my talk, I will raise research challenges for how to make cyber-physical systems trustworthy.

Wednesday, September 7, 10:00 - 10:15

Coffee Break

Wednesday, September 7, 10:15 - 11:15

Plenary I

The Internet of Important Things
Edward A. Lee, Robert S. Pepper Distinguished Professor, UC Berkeley, USA
Room: Courtyard Ballroom
Chair: Danella Zhao (Old Dominion University, USA)

Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Applications include manufacturing, transportation, energy production and distribution, biomedical, smart buildings, and military systems, to name a few. Increasingly, today, such systems leverage Internet technology, despite a significant mismatch in technical objectives. A major challenge today is to make this technology reliable, predictable, and controllable enough for "important" things, such as safety-critical and mission-critical systems. In this talk, I will analyze how emerging technologies can translate into better models and better engineering methods for this evolving Internet of important things. I will particularly focus on embedded processor design that can significantly improve determinism and reduce power consumption for embedded software.

Wednesday, September 7, 11:20 - 12:35

Best Paper Award I

Room: Municipal
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)
11:20 Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing
Shu Hokimoto, Tohru Ishihara and Hidetoshi Onodera (Kyoto University, Japan)
11:45 Digital LDO Modeling for Early Design Space Exploration
Stefan Leitner (Southern Illinois University Carbondale); Paul West, Chao Lu and Haibo Wang (Southern Illinois University Carbondale, USA)
12:10 A Digital-circuit-based Evolutionary-computation Algorithm for Time-interleaved ADC Background Calibration
Dadian Zhou (Texas A&M University, USA); Claudio Talarico (Gonzaga University, USA); Jose Silva-Martinez (Texas A&M University, USA)

Design Track

Room: Superior
Chair: Gururaj Shamanna (Qualcomm, USA)
11:20 Design Challenges and Practical Solutions for a Mobile SoC in the 10nm FinFET Process
11:35 Design Challenges in a Low-Power Management Unit for a GNSS Receiver System in 28nm CMOS
Filippo Maria Neri, Thomas Brauner and Eric De Mey (U-blox AG); Christian Schippel (Globalfoundries, Germany)
11:50 Intelligent Low Power Wake-Up Protocol for Multi-Regulator Power Management Architectures
Sunny Gupta (Freescale Semiconductor India (NXP), India); Kumar Abhishek (NXP, USA); Nitin Pant, Garima Sharda and Gautham Shivender Harinarayan (Freescale Semiconductor India (NXP), India)
12:05 Efficient Circuit Architecture and FPGA Implementation for LTE Single Carrier FDMA DFT
J Greg Nash (Centar LLC, USA)
12:20 Energy Efficient Design of Ultra-Lightweight Hardware Security Circuits for IoT Applications
Vikram Suresh (Intel Corporation); Sudhir Satpathy, Sanu Mathew and Ram Krishnamurthy (Intel Corporation, USA)

RF, Analog Design I

Room: Federal
Chair: Andrew Marshall (University of Texas at Dallas, USA)
11:20 Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Applications
Jr-Ming Chen (Nation Chiao Tung University, Taiwan); Po-Tsang Huang (National Chiao Tung University); Shang-Lin Wu (Nation Chiao Tung University, Taiwan); Wei Hwang and Ching-Te Chuang (National Chiao Tung University, Taiwan)
11:45 A 12 Bit Split-Array Switched Capacitor Power Amplifier in 130nm CMOS
12:10 Low-Jitter All-Digital Phase-Locked Loop with Novel PFD and High Resolution TDC & DCO
Xiaoying Deng, Yanyan Mo, Xin Lin and Mingcheng Zhu (Shenzhen University, P.R. China)

Wednesday, September 7, 12:35 - 14:00

Lunch

Wednesday, September 7, 14:00 - 15:40

Industry Forum: IoT for Real Life Part I

Room: Municipal
Chairs: Ram Krishnamurthy (Intel Corporation, USA), Magdy Bayoumi (University of Louisiana, USA)

14:00 - 14:05: Opening by Chair
14:05 - 14:20: IoT: From Vision to Reality (Magdy Bayoumi, University of Louisiana at Lafayette)
14:20 - 14:50: IoT: Design Challenges and Opportunities (Danielle Griffith, TI)
14:50 - 15:35: IoT: No more Moore? Let's break the law! (Wolf Richter, President, EPIC Semiconductor)

SoC Design Methods and Algorithms I

Room: Federal
Chair: Claudio Talarico (Gonzaga University, USA)
14:00 Statistical Design Attribute Identification for FinFET Outlier and Silicon-to-SPICE Gap
Hyosig Won and Katsuhiro Shimazu (Samsung Electronics, Korea)
14:25 Intra-chip Traffic Generation Under Autoregressive Models Based on Time Series Obtained by TLM Simulation
Jose E Bueno (Universidade Estadual de Campinas, Brazil); Jorge Gonzalez (University of Campinas, Brazil); Wang Chau (University of Sao Paulo)
14:50 A Method to Estimate Effectiveness of Weak Bit Test: Comparison of Weak pMOS and WL Boost Based Test - 28nm FDSOI Implementation
Nidhi Batra, Shashwat Kaushik and Anil Gundu Kumar (IIIT Delhi, India); Mohammad Hashmi (IIIT Delhi); Anuj Grover (ST Microelectronics, India); Gangaikondan Visweswaran (IIIT Delhi, India)
15:15 CATBR-Congestion Aware Traffic Bridging Routing Among Hierarchical Networks-on-Chip
Mingmin Bai (University of Louisiana at Lafayette, USA); Danella Zhao and Hongyi Wu (Old Dominion University, USA)

Special Session: Emerging Trends in SoC Testing

Room: Superior
Chair: Yu Huang (Mentor Graphics, USA)
14:00 EDT Dynamic Bandwidth Management in SoC Testing
Yu Huang (Mentor Graphics, USA)
14:25 Toward More Efficient Scan Data Bandwidth Utilization on Modern SOCs
14:50 In-Field System-Health Monitoring Based on IEEE 1687
Farrokh Ghani Zadegan, Dimitar Nikolov and Erik Larsson (Lund University, Sweden)
15:15 High Bandwidth Packetized DFT Fabric for Servers and SoCs
Glenn Colon-Bonet (Intel Corporation, USA)

Wednesday, September 7, 15:40 - 16:00

Coffee Break

Wednesday, September 7, 16:00 - 17:40

Application Specific SoC Designs

Room: Superior
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)
16:00 Novel Lightweight FF-APUF Design for FPGA
Chongyan Gu (Queen's University Belfast, United Kingdom (Great Britain)); Yijun Cui (Nanjing University of Aeronautics and Astronautics, P.R. China); Neil Hanley and Maire O'Neill (Queen's University Belfast, United Kingdom (Great Britain))
16:25 Efficient VLSI Architecture for SAO Decoding in 4K Ultra-HD HEVC Video Codec
Mihir N Mody, Niraj Nandan and Hetul Sanghvi (Texas Instruments, Inc.)
16:50 A Flexible Router Architecture for Three-Dimensional Network-on-Chips
Mostafa Khamis (Mentor Graphics, Egypt); Mostafa Said Abdelrehim (Sun Yat-sen University-Carnegie Mellon University (SYSU-CMU) Joint Institute of Engineering, Guangzhou, China); Ahmed Shalaby (Faculty of Computers and Informatics, Benha University & Egypt-Japan University for Science and Technology, Egypt)
17:15 Single-ended D Flip-Flop with Implicit Scan Mux for High Performance Mobile AP

Emerging and Evolutionary Design Algorithms

Room: Federal
Chair: Visvesh Sathe (University of Washington at Seattle, USA)
16:00 Multi-Objective Sample Preparation Algorithm for Microfluidic Biochips Supporting Various Mixing Models
Yung-Chun Lei (National Chiao Tung University, Taiwan); Tung-Hsuan Lin (MediaTek Inc., Taiwan); Juinn-Dar Huang (National Chiao Tung University, Taiwan)
16:25 A Multiplication Reduction Technique with Near-Zero Approximation for Embedded Learning in IoT Devices
Yuxiang Huan (Fudan University); Yifan Qin (Fudan University, P.R. China); Yantian You (KTH-The Royal Institute of Technology); Lirong Zheng (Fudan University, P.R. China); Zhuo Zou (Fudan University & KTH Royal Institute of Technology, Sweden)
16:50 Feature Study on a Programmable Network Traffic Classifier
Keissy Guerra Perez (Queen University of Belfast, United Kingdom (Great Britain)); Xin Yang and Sandra Scott-Hayward (Queen's University Belfast, United Kingdom (Great Britain)); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain))
17:15 Design and ASIC Acceleration of Cortical Algorithm for Text Recognition
Sumon Dey and Paul Franzon (North Carolina State University, USA)

Industry Forum: IoT for Real Life Part II

Room: Municipal
Chairs: Ram Krishnamurthy (Intel Corporation, USA), Magdy Bayoumi (University of Louisiana, USA)

16:00 - 16:30: Machine Learning Accelerators for IoTs (Ram Krishnamurthy, Intel Corp)
16:30 - 17:00: IoT System Level Challenges and Applications (Ramalingam Sridhar, SUNY at Buffalo)
17:00 - 17:30: Interactive session with all the speakers
17:30 - 17:40: Closing by Chair

Wednesday, September 7, 18:00 - 19:30

Poster Session & Reception

Room: Courtyard Foyer
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)
A 200 MS/s 8-bit Time-Based Analog-to-Digital Converter with Inherit Sample and Hold
Ali H. Hassan (Cairo University); Mohammed Ismail (Cairo University, Egypt); Yehea Ismail (American University in Cairo, Egypt); Hassan Mostafa (University of Toronto, Canada)
A 0.4V 320Mb/s 28.7μW 1024-bit Configurable Multiplier for Subthreshold SOC Encryption
Weiwei Shi (Shenzhen University & The Chinese University of Hong Kong, P.R. China); Chiu-sing Oliver Choy (The Chinese University of Hong Kong)
Low Voltage Flash Memory Design Based on Floating Gate SOFFET
Emeshaw Ashenafi (University of Missouri-Kansas City, USA); Azzedin Es-Sakhi (University of Missouri – Kansas City, USA); Masud H Chowdhury (University of Illinois at Chicago, USA)
Hardware Implementation of Hierarchical Temporal Memory Algorithm
Weifu Li and Paul Franzon (North Carolina State University, USA)
An Early Global Routing Framework for Uniform Wire Distribution in SoCs
Bapi Kar (Indian Institute of Technology, Kharagpur); Susmita Sur-Kolay (ISI Kolkata, India); Chittaranjan Mandal (Indian Institute of Technology, Kharagpur, India)
SAMi: Self-Aware Migration Approach for Congestion Reduction in NoC-based MCSoC
Amin Rezaei (University of Louisiana at Lafayette, USA); Masoud Daneshtalab (KTH Royal Institute of Technology, Sweden); Danella Zhao (Old Dominion University, USA); Mehdi Modarressi (University of Tehran, Iran)
Modeling and Optimization of the Bond-Wire Interface in a Hybrid CMOS-Photonic Traveling-Wave MZM Transmitter
Kehan Zhu (Boise State University, USA); Vishal Saxena (University of Idaho, USA); Xinyu Wu (Boise State University, USA)
A Jitter Cancellation Circuit for High Speed I/O Interfaces
A CMOS Analog Front-End for Driving a High-Speed SAR ADC in Low-Power Ultrasound Imaging Systems
Taehoon Kim, Han Yang, Sangmin Shin, Hyongmin Lee and Suhwan Kim (Seoul National University, Korea)
Behavioral Modeling of Drain Current of an Avalanche ISFET Near Breakdown Voltage
Mohammad Uzzal and Payman Zarkesh-Ha (University of New Mexico, USA); Paul Szauter (ElectroSeq); Jeremy Edwards (University of New Mexico)
A Novel Power Reduction Technique Using Wire Multiplexing
Mostafa Said Abdelrehim (Sun Yat-sen University-Carnegie Mellon University (SYSU-CMU) Joint Institute of Engineering, Guangzhou, China); Hossam Hassan and HyungWon Kim (Chungbuk National University & College of Electrical and Computer Engineering, Korea)
An Ultra-Low Power Voltage-to-Time Converter (VTC) Circuit for Low Power and Low Speed Applications
Hassan Mostafa (University of Toronto, Canada); Ali H. Hassan (Cairo University); Tawfik Ismail (NILES, Cairo University, Egypt); Salam Gabran (University of Waterloo, Canada)
Automated Full Chip SPICE Simulations with Self-Checking Assertions for Last Mile Verification & First Pass Silicon of Mixed Signal SoCs
Analytical Noise Model for Avalanche ISFET Sensor Suitable for Next Generation Sequencing
Mohammad Uzzal and Payman Zarkesh-Ha (University of New Mexico, USA); Paul Szauter (ElectroSeq); Jeremy Edwards (University of New Mexico)
Rotator-Based Multiplexer Network Synthesis for Field-Data Extractors
Koki Ito and Kazushi Kawamura (Waseda University, Japan); Yutaka Tamiya (Fujitsu Laboratories Ltd., Japan); Masao Yanagisawa and Nozomu Togawa (Waseda University, Japan)
A Comparator Timing Assisted SAR ADC Technique with Reduced Conversion Cycles
Abhilash Karnatakam Nagabhushana (Southern Illinois University Carbondale); Haibo Wang (Southern Illinois University Carbondale, USA)
Efficient Implementation of the AES Algorithm for Security Applications
High-Voltage Low-Power Startup Backup Battery Switch Using Low Voltage Devices in 28nm CMOS
Filippo Maria Neri (U-blox AG); Craig Keogh (U-blox AG, Switzerland); Thomas Brauner and Eric De Mey (U-blox AG); Christian Schippel (Globalfoundries, Germany)

Thursday, September 8

Thursday, September 8, 07:30 - 08:30

Breakfast

Thursday, September 8, 08:30 - 09:30

Keynote II

SoX at the Edge: the Heterogeneous, Highly Integrated IoT Systems of the future
Mircea Stan, Professor, University of Virginia, USA
Room: Courtyard Ballroom
Chair: Danella Zhao (Old Dominion University, USA)

Rumors of Moore's Law demise have been greatly exaggerated! While transistors are not getting simultaneously smaller, faster and lower power every couple of years like for the past several decades, inexorable forces to cram more devices together are still running strong, except that they are now pushing upwards in the third dimension. Heterogeneity, monolithic vs. TSV-based scaling for 3D, and closing the energy loop (cooling and power delivery) will punctuate this talk as it explores the challenges and opportunities that IoT systems of the future face as they move away from planar Systems-on-Chip (SoC) to becoming three dimensional Systems-on-Anything (SoX, e.g. Systems-on-Package, Systems-on-Interposer, etc.)

Thursday, September 8, 09:30 - 10:30

Plenary II

Energy-Efficient and Ultra Low Voltage Design pf Sub-14nm SoCs and Microprocessors: Challenges and Opportunities
Ram Krishnamurthy, Senior Principal Engineer, Intel Labs, USA
Room: Courtyard Ballroom
Chair: Danella Zhao (Old Dominion University, USA)

This talk presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as encryption, graphics and media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra mobile SoCs, dynamic on-the fly configurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.

Thursday, September 8, 10:30 - 10:45

Coffee Break

Thursday, September 8, 10:45 - 12:00

Best Paper Award II

Room: Superior
Chair: Karan Singh Bhatia (Texas Instruments, Inc., USA)
10:45 Design of a Power-Efficient ARM Processor with a Timing-Error Detection and Correction Mechanism
Sao-Jie Chen, Grace Liu, Hsin-Ping Yang and Cheng-Hao Luo (National Taiwan University, Taiwan); Wen-Mei Hwu (University of Illinois at Urbana-Champaign, USA)
11:10 Compressive Image Sensor Technique with Sparse Measurement Matrix
Stefan Leitner (Southern Illinois University Carbondale); Haibo Wang (Southern Illinois University Carbondale, USA); Spyros Tragoudas (Southern Illinois University, Carbondale, USA)
11:35 Performance Optimization and Power Efficiency in 3D IC with Buffer Insertion Scheme
Mohammad Ahmed, Sucheta Mohapatra and Malgorzata Chrzanowska-Jeske (Portland State University, USA)

Industry Forum: Data Analytics and Security in IoT Part I

Room: Municipal
Chairs: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain)), Ravi Mukkamala (Old Dominion University, USA)

10:45 - 10:50: Opening by Chair
10:50 - 11:15: Introduction (Sakir Sezer, Queen's University Belfast & CTO Titan IC, United Kingdom)
11:15 - 12:00: SoC Challenges Enabling Server-based Networking (Ron Swartzentruber, Senior Principal Engineer, Netronome)

Special Session: SoC Architectures for Machine Learning through Inexactness

Room: Federal
Chairs: Seongsoo Hong (Seoul National University, Korea), Anshumali Shrivastava (Rice University, USA)
10:45 SoC Architectures for Machine Learning Through Inexactness
Seongsoo Hong (Seoul National University, Korea); Anshumali Shrivastava (Rice University, USA)
11:03 CaPSuLe: A Camera-based Positioning System Using Learning
Yongshik Moon, Soonhyun Noh and Daedong Park (Seoul National University, Korea); Chen Luo and Anshumali Shrivastava (Rice University, USA); Seongsoo Hong (Seoul National University, Korea); Krishna Palem (Rice University, USA)
11:22 Overcoming the Power Wall by Exploiting Inexactness and Emerging COTS Architectural Features Trading Precision for Improving Application Quality
Mike Fagan (Rice University, USA); Jeremy Schlachter (Ecole Polytechnique Federale de Lausanne, Switzerland); Kazutomo Yoshii and Sven Leyffer (Argonne National Laboratory, USA); Krishna Palem (Rice University, USA); Marc Snir (Argonne National Laboratories, USA); Stefan Wild (Argonne National Laboratory, USA); Christian Enz (Ecole Polytechnique Federale de Lausanne, Switzerland)
11:41 Low-Power Real-Time Intelligent SoCs for Smart Machines
Youchang Kim (KAIST, Korea); Injoon Hong and Seongwook Park (Korea Advanced Institute of Science and Technology (KAIST), Korea); Hoi-Jun Yoo (KAIST, Korea)

Thursday, September 8, 12:00 - 13:30

Lunch

Thursday, September 8, 13:30 - 15:10

Advanced SoC Components

Room: Federal
Chair: Andrew Marshall (University of Texas at Dallas, USA)
13:30 Standard Cell Library Based Layout Characterization and Power Analysis for 10nm Gate-All-Around (GAA) Transistors
Luhao Wang, Tiansong Cui and Shahin Nazarian (University of Southern California, USA); Yanzhi Wang (Syracuse University, USA); Massoud Pedram (University of Southern California, USA)
13:55 Comparative Analysis of Hybrid Magnetic Tunnel Junction and CMOS Logic Circuits
Darya Almasi (San Francisco State University, USA); Houman Homayoun (George Mason University, USA); Hassan Salmani (Howard University, USA); Hamid Mahmoodi (San Francisco State University, USA)
14:20 Modeling and Simulation of Quantum-Well Infrared Photodetectors
Sao-Jie Chen, Hsin-Ping Yang, Ding-Jyun Lin and Grace Liu (National Taiwan University, Taiwan)
14:45 Sensitivity Analysis for SoC Performance Benchmark Against Interconnect Parasitic Resistance and Capacitance Beyond 10-nm FinFET Technology

Industry Forum: Data Analytics and Security in IoT Part II

Room: Municipal
Chairs: Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom (Great Britain)), Ravi Mukkamala (Old Dominion University, USA)

13:30 - 14:15: Safe Planning and Control Under Uncertainty (Ashish Kapoor, Senior Researcher, Microsoft Research)
14:15 - 15:00: In Silicon We Trust - How to Fix the Internet of Broken Things (Cesare Garlati, Chief Security Strategist, prpl Foundation)
15:00 - 15:10: Interactive session with all the speakers
15:10: Closing by chair

RF, Analog Design II

Room: Superior
Chair: Haibo Wang (Southern Illinois University Carbondale, USA)
13:30 A Low Power Fourth Order ΣΔ CMOS Modulator with Subthreshold Amplifier
Kwang S. Yoon and Jae-Hyeon Seong (Inha University, Korea); Soo-Hun Yang (Silicon Works, Korea)
13:55 A Novel Design of a Dual Functionality Read-Write Driver for SRAM
Pulkit Sharma (IIITD); Mohammad Hashmi (IIITD, India)
14:20 Novel Ultra Low Voltage Mobile Compatible RF MEMS Switch for Reconfigurable Microstrip Antenna
Hassan Mostafa (University of Toronto, Canada); Moez El-Massry and Moataz Medhat (Cairo University, Egypt)

Thursday, September 8, 15:10 - 15:30

Coffee Break

Thursday, September 8, 15:30 - 17:00

Panel Discussion: Spreading intelligence across a trillion devices and making the most of it - How pervasive will sensemaking be in IoT, and which applications will take advantage of it?

Room: Courtyard Ballroom
Chairs: Massimo Alioto (National University of Singapore, Singapore), Magdy Bayoumi (University of Louisiana at Lafayette, USA)

PANELISTS:
Ron Swartzentruber (Senior Principal Engineer, Netronome)
Lubna Dajani (Chief Strategy Officer, Intercede)
Ram Krishnamurthy (Senior Principal Engineer, Intel)
Mircea Stan (Professor, University of Virginia)
Yong Lian (Professor, York University)

Thursday, September 8, 17:30 - 18:30

Cocktail Reception

Room: Vista
Chair: Danella Zhao (Old Dominion University, USA)

Thursday, September 8, 18:30 - 21:00

Conference Banquet

Art Swift (President of prpl Foundation)
Room: Visions (28th Floor)
Chair: Danella Zhao (Old Dominion University, USA)

Friday, September 9

Friday, September 9, 07:30 - 08:30

Breakfast

Friday, September 9, 08:30 - 10:10

Intel Training Workshop Part I

Altera SDK for OpenCL for Embedded Applications on FPGAs
Marlon Price, Intel Programmable Solutions Group, USA
Room: Municipal
Chair: Marlon Price (Altera, USA)

This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and performance optimization features that keep the development time short and productivity high.

SoC Design Methods and Algorithms II

Room: Federal
Chair: Juergen Becker (Karlsruhe Institute of Technology, Germany)
08:30 Heterogeneous Memory Assembly Exploration Using a Floorplan and Interconnect Aware Framework
Prakhar Raj Gupta (Indian Institute of Technology, Delhi & ST Microelectronics India, India); Gaurav Narang (STMicroelectronics, India); Gangaikondan Visweswaran (Indian Institute of Technology, Delhi); Anuj Grover (ST Microelectronics, India)
08:55 Variable-Length VLIW Encoding for Code Size Reduction in Embedded Processors
Ting-Yu Shyu (National Chung Cheng University); Bo-Yu Su (National Chung Cheng University, Taiwan); Tay-Jyi Lin (National Chung Cheng University, Taiwan); Chingwei Yeh (National Chung-Cheng University, Taiwan); Tien-Fu Chen (National Chiao Tung University, Taiwan); Jinn-Shyan Wang (National Chung Cheng University, Taiwan)
09:20 Self-dual Diamond-graph CMOS H-bridge Logic Family
Shun-Wen Cheng (Far East University, Taiwan)
09:45 ERFAN: Efficient Reconfigurable Fault-Tolerant Deflection Routing Algorithm for 3-D Network-on-Chip
Somayeh Maabi (Shaid Beheshti University, Iran); Farshad Safaei (Shahid Beheshti University, Iran); Amin Rezaei (University of Louisiana at Lafayette, USA); Masoud Daneshtalab (KTH Royal Institute of Technology, Sweden); Danella Zhao (Old Dominion University, USA)

Special Session: Emerging Stochastic Computing and Neuromorphic Computing: Arithmetic, Algorithm, and Applications

Room: Superior
Chair: Yanzhi Wang (Syracuse University, USA)
08:30 Design of High-speed Low-power Polar BP Decoder Using Emerging Technologies
Ao Ren (Syracuse University, USA); Bo Yuan (City University of New York, USA); Yanzhi Wang (Syracuse University, USA)
08:55 A Low-Computation-Complexity, Energy-Efficient, and High-Performance Linear Program Solver Using Memristor Crossbars
Ruizhe Cai, Ao Ren, Yanzhi Wang, Sucheta Soundarajan and Qinru Qiu (Syracuse University, USA); Bo Yuan (City University of New York, USA); Paul Bogdan (University of Southern California, USA)
09:20 Efficient Hardware Architecture of Softmax Layer in Deep Neural Network
Bo Yuan (City University of New York, USA)
09:45 Noisy Neuromorphic Circuit Modeling Obsessive Compulsive Disorder
Saeid Barzegarjalal, Kun Yue and Alice C. Parker (University of Southern California, USA)

Friday, September 9, 10:10 - 10:30

Coffee Break

Friday, September 9, 10:30 - 12:10

Intel Training Workshop Part II

Altera SDK for OpenCL for Embedded Applications on FPGAs
Marlon Price, Intel Programmable Solutions Group, USA
Room: Municipal
Chair: Marlon Price (Altera, USA)

This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and performance optimization features that keep the development time short and productivity high.

Low Power Design

Room: Federal
Chair: Sao-Jie Chen (National Taiwan University, Taiwan)
10:30 Practical Power Consumption Analysis with Current Smartphones
Xiang Chen (George Mason University, USA); Kent Nixon and Yiran Chen (University of Pittsburgh, USA)
10:55 Fully Parallel Content Addressable Memory Design Using Multi-Bank Structure
Shixiong Jiang (University at Buffalo, USA); Vijayalakshmi Saravanan (University at Buffalo); Pengzhan Yan and Ramalingam Sridhar (University at Buffalo, USA)
11:20 New Power Budgeting and Thermal Management Scheme for Multi-Core Systems in Dark Silicon
Hai Wang and Ming Zhang (University of Electronic Science and Technology of China, P.R. China); Sheldon Tan (University of California, Riverside, USA); Chi Zhang and Yuan Yuan (University of Electronic Science and Technology of China, P.R. China); Keheng Huang and Zhenghong Zhang (Southwest China Research Institute of Electronic Equipment, P.R. China)
11:45 Overoptimistic Voltage Scaling in Pre-Error AVS Systems and Learning-Based Alleviation
Yi-Hsuan Ting (National Chung Cheng University, Taiwan); Chih-Yang Wang (National Tsing Hua University, Taiwan); Yu-Sian Chang and Tay-Jyi Lin (National Chung Cheng University, Taiwan); Shih-Chieh Chang (National Tsing Hua University); Jinn-Shyan Wang (National Chung Cheng University, Taiwan)

Special Session: Security and Validation in Mobile, Embedded, and IoT Systems

Room: Superior
Chair: Sandip Ray (NXP Semiconductors, USA)
10:30 Security Challenges in Mobile and IoT Systems
Sandip Ray (NXP Semiconductors, USA); Jayanta Bhadra (NXP Semiconductors)
10:50 Quantifying Trust in Autonomous System Under Uncertainties
Raj Gautam Dutta and Xiaolong Guo (University of Central Florida, USA); Yier Jin (University of Florida, USA)
11:10 Striking a Balance Between SoC Security and Debug Requirements
Wen Chen and Jayanta Bhadra (NXP Semiconductor, USA)
11:30 Can We Bell the CAD?
Jeyavijayan Rajendran (University of Texas at Dallas, USA)
11:50 Mobile Connected Devices: Security Challenges and Opportunities
Joe Hendrix (Galois Inc., USA)

Friday, September 9, 12:10 - 13:00

Lunch

Friday, September 9, 13:00 - 17:30

Post Conference Event: The Museum of Flight Tour (not included in registration)

More information and ticket booking here: http://www.ieee-socc.org/program-info/social-program

Enjoy the wonder of flight in one of Seattle's most spectacular settings. Walk the aisle of JFK's Air Force One and climb aboard the West Coast's only Concorde. Revel in the history and heroics of WWI and WWII. Barrel-roll a Mustang, land on the moon, and soar over Puget Sound in a simulator. Experience the excitement of the space race and sit at the controls of the world's fastest jet. From the Wright brothers to the exploration of Mars, you'll find it at The Museum of Flight!

This 15-acre campus includes over 160 air and spacecraft, the original Boeing Aircraft factory, flight simulators, and dozens of fun, interactive exhibits and family activities. From the world's oldest fighter plane to the supersonic Concorde, the only full-scale NASA Space Shuttle Trainer and the beautiful Boeing 787 Dreamliner, you'll see the machines and experience the stories of those who flew them. The unique, 3-acre Aviation Pavillion offers the dramatic development of large aircraft in an open-air gallery with a cafe and children's playground.

This tour is not included in your conference registration. Ticket Price: $37 + tax/ticketing fee, includes transportation and admission to the museum.