Program for 2016 29th IEEE International System-on-Chip Conference (SOCC)
Tuesday, September 6
Tuesday, September 6, 08:00 - 09:00
Breakfast
Tuesday, September 6, 09:00 - 10:30
Tutorial 1A: Design Challenges for the Internet of Things
Tutorial 1B: Transistors: Past, Present and Future
Tuesday, September 6, 10:30 - 10:45
Coffee Break
Tuesday, September 6, 10:45 - 12:15
Tutorial 2A: 3D Integration - Challenges and Advantages
Tutorial 2B: CMOS Integrated System on a Chip for Neural Interface Applications
Tuesday, September 6, 12:15 - 14:00
Lunch
Tuesday, September 6, 14:00 - 15:30
Tutorial 3A: Bringing Cores Closer Together: The Wireless Revolution in On-Chip Communication
Tutorial 3B: The Design Challenges for Self-Powered Wireless Wearable ECG Sensor SoC
Tuesday, September 6, 15:30 - 15:45
Coffee Break
Tuesday, September 6, 15:45 - 17:15
Tutorial 4A: Supply Voltage Noise and Mitigation for Real World SoCs
Tutorial 4B: ADC Design - From System Architecture to Transistor Level Design
Wednesday, September 7
Wednesday, September 7, 07:30 - 08:30
Breakfast
Wednesday, September 7, 08:30 - 08:45
Opening Remarks
Wednesday, September 7, 08:45 - 09:00
Technical Program Overview
Wednesday, September 7, 09:00 - 10:00
Opening Keynote
Cyber-physical systems are engineered systems that require tight conjoining of and coordination between the computational (discrete) and the physical (continuous). Cyber-physical systems are rapidly penetrating every aspect of our lives, with potential impact on sectors critical to national security and competitiveness, including aerospace, automotive, chemical production, civil infrastructure, energy, finance, healthcare, manufacturing, materials, and transportation. As these systems fulfill the promise of the Internet of Things, smart cities, household robots, and personalized medicine, we need to ensure they are trustworthy: reliable, secure, and privacy-preserving. This talk will look at cyber-physical systems from the lens of trustworthy computing. Throughout my talk, I will raise research challenges for how to make cyber-physical systems trustworthy.
Wednesday, September 7, 10:00 - 10:15
Coffee Break
Wednesday, September 7, 10:15 - 11:15
Plenary I
Cyber-physical systems are integrations of computation, communication networks, and physical dynamics. Applications include manufacturing, transportation, energy production and distribution, biomedical, smart buildings, and military systems, to name a few. Increasingly, today, such systems leverage Internet technology, despite a significant mismatch in technical objectives. A major challenge today is to make this technology reliable, predictable, and controllable enough for "important" things, such as safety-critical and mission-critical systems. In this talk, I will analyze how emerging technologies can translate into better models and better engineering methods for this evolving Internet of important things. I will particularly focus on embedded processor design that can significantly improve determinism and reduce power consumption for embedded software.
Wednesday, September 7, 11:20 - 12:35
Best Paper Award I
- 11:20 Minimum Energy Point Tracking Using Combined Dynamic Voltage Scaling and Adaptive Body Biasing
- 11:45 Digital LDO Modeling for Early Design Space Exploration
- 12:10 A Digital-circuit-based Evolutionary-computation Algorithm for Time-interleaved ADC Background Calibration
Design Track
- 11:20 Design Challenges and Practical Solutions for a Mobile SoC in the 10nm FinFET Process
- 11:35 Design Challenges in a Low-Power Management Unit for a GNSS Receiver System in 28nm CMOS
- 11:50 Intelligent Low Power Wake-Up Protocol for Multi-Regulator Power Management Architectures
- 12:05 Efficient Circuit Architecture and FPGA Implementation for LTE Single Carrier FDMA DFT
- 12:20 Energy Efficient Design of Ultra-Lightweight Hardware Security Circuits for IoT Applications
RF, Analog Design I
- 11:20 Area-Power-Efficient 11-Bit Hybrid Dual-Vdd ADC with Self-Calibration for Neural Sensing Applications
- 11:45 A 12 Bit Split-Array Switched Capacitor Power Amplifier in 130nm CMOS
- 12:10 Low-Jitter All-Digital Phase-Locked Loop with Novel PFD and High Resolution TDC & DCO
Wednesday, September 7, 12:35 - 14:00
Lunch
Wednesday, September 7, 14:00 - 15:40
Industry Forum: IoT for Real Life Part I
14:00 - 14:05: Opening by Chair
14:05 - 14:20: IoT: From Vision to Reality (Magdy Bayoumi, University of Louisiana at Lafayette)
14:20 - 14:50: IoT: Design Challenges and Opportunities (Danielle Griffith, TI)
14:50 - 15:35: IoT: No more Moore? Let's break the law! (Wolf Richter, President, EPIC Semiconductor)
SoC Design Methods and Algorithms I
- 14:00 Statistical Design Attribute Identification for FinFET Outlier and Silicon-to-SPICE Gap
- 14:25 Intra-chip Traffic Generation Under Autoregressive Models Based on Time Series Obtained by TLM Simulation
- 14:50 A Method to Estimate Effectiveness of Weak Bit Test: Comparison of Weak pMOS and WL Boost Based Test - 28nm FDSOI Implementation
- 15:15 CATBR-Congestion Aware Traffic Bridging Routing Among Hierarchical Networks-on-Chip
Special Session: Emerging Trends in SoC Testing
- 14:00 EDT Dynamic Bandwidth Management in SoC Testing
- 14:25 Toward More Efficient Scan Data Bandwidth Utilization on Modern SOCs
- 14:50 In-Field System-Health Monitoring Based on IEEE 1687
- 15:15 High Bandwidth Packetized DFT Fabric for Servers and SoCs
Wednesday, September 7, 15:40 - 16:00
Coffee Break
Wednesday, September 7, 16:00 - 17:40
Application Specific SoC Designs
- 16:00 Novel Lightweight FF-APUF Design for FPGA
- 16:25 Efficient VLSI Architecture for SAO Decoding in 4K Ultra-HD HEVC Video Codec
- 16:50 A Flexible Router Architecture for Three-Dimensional Network-on-Chips
- 17:15 Single-ended D Flip-Flop with Implicit Scan Mux for High Performance Mobile AP
Emerging and Evolutionary Design Algorithms
- 16:00 Multi-Objective Sample Preparation Algorithm for Microfluidic Biochips Supporting Various Mixing Models
- 16:25 A Multiplication Reduction Technique with Near-Zero Approximation for Embedded Learning in IoT Devices
- 16:50 Feature Study on a Programmable Network Traffic Classifier
- 17:15 Design and ASIC Acceleration of Cortical Algorithm for Text Recognition
Industry Forum: IoT for Real Life Part II
16:00 - 16:30: Machine Learning Accelerators for IoTs (Ram Krishnamurthy, Intel Corp)
16:30 - 17:00: IoT System Level Challenges and Applications (Ramalingam Sridhar, SUNY at Buffalo)
17:00 - 17:30: Interactive session with all the speakers
17:30 - 17:40: Closing by Chair
Wednesday, September 7, 18:00 - 19:30
Poster Session & Reception
- A 200 MS/s 8-bit Time-Based Analog-to-Digital Converter with Inherit Sample and Hold
- A 0.4V 320Mb/s 28.7μW 1024-bit Configurable Multiplier for Subthreshold SOC Encryption
- Low Voltage Flash Memory Design Based on Floating Gate SOFFET
- Hardware Implementation of Hierarchical Temporal Memory Algorithm
- An Early Global Routing Framework for Uniform Wire Distribution in SoCs
- SAMi: Self-Aware Migration Approach for Congestion Reduction in NoC-based MCSoC
- Modeling and Optimization of the Bond-Wire Interface in a Hybrid CMOS-Photonic Traveling-Wave MZM Transmitter
- A Jitter Cancellation Circuit for High Speed I/O Interfaces
- A CMOS Analog Front-End for Driving a High-Speed SAR ADC in Low-Power Ultrasound Imaging Systems
- Behavioral Modeling of Drain Current of an Avalanche ISFET Near Breakdown Voltage
- A Novel Power Reduction Technique Using Wire Multiplexing
- An Ultra-Low Power Voltage-to-Time Converter (VTC) Circuit for Low Power and Low Speed Applications
- Automated Full Chip SPICE Simulations with Self-Checking Assertions for Last Mile Verification & First Pass Silicon of Mixed Signal SoCs
- Analytical Noise Model for Avalanche ISFET Sensor Suitable for Next Generation Sequencing
- Rotator-Based Multiplexer Network Synthesis for Field-Data Extractors
- A Comparator Timing Assisted SAR ADC Technique with Reduced Conversion Cycles
- Efficient Implementation of the AES Algorithm for Security Applications
- High-Voltage Low-Power Startup Backup Battery Switch Using Low Voltage Devices in 28nm CMOS
Thursday, September 8
Thursday, September 8, 07:30 - 08:30
Breakfast
Thursday, September 8, 08:30 - 09:30
Keynote II
Rumors of Moore's Law demise have been greatly exaggerated! While transistors are not getting simultaneously smaller, faster and lower power every couple of years like for the past several decades, inexorable forces to cram more devices together are still running strong, except that they are now pushing upwards in the third dimension. Heterogeneity, monolithic vs. TSV-based scaling for 3D, and closing the energy loop (cooling and power delivery) will punctuate this talk as it explores the challenges and opportunities that IoT systems of the future face as they move away from planar Systems-on-Chip (SoC) to becoming three dimensional Systems-on-Anything (SoX, e.g. Systems-on-Package, Systems-on-Interposer, etc.)
Thursday, September 8, 09:30 - 10:30
Plenary II
This talk presents some of the prominent barriers to designing energy-efficient circuits in the sub-14nm CMOS technology regime and outlines new paradigm shifts necessary in next-generation multi-core microprocessors and systems-on-chip. Emerging trends and key challenges in sub-14nm design are outlined, including (i) device and on-chip interconnect technology projections, (ii) performance, leakage and voltage scalability, (iii) special-purpose hardware accelerators and reconfigurable co-processors for compute-intensive signal processing algorithms, (iv) fine-grain power management with integrated voltage regulators, and (v) resilient circuit design to enable robust variation-tolerant operation. Energy-efficient arithmetic and logic circuit techniques, static/dynamic supply scaling, on-die interconnect fabric circuits, ultra-low-voltage and near-threshold logic and memory circuit techniques, and multi-supply/multi-clock domain design for switching and leakage energy reduction are described. Special purpose hardware accelerators and data-path building blocks for enabling high GOPS/Watt on specialized DSP tasks such as encryption, graphics and media processing are presented. Power efficient optimization of microprocessors to span a wide operating range across high performance servers to ultra mobile SoCs, dynamic on-the fly configurability and adaptation, and circuit techniques for active/standby-mode leakage reduction with robust low-voltage operability are reviewed. Specific chip design examples and case studies supported by silicon measurements and trade-offs will be discussed.
Thursday, September 8, 10:30 - 10:45
Coffee Break
Thursday, September 8, 10:45 - 12:00
Best Paper Award II
- 10:45 Design of a Power-Efficient ARM Processor with a Timing-Error Detection and Correction Mechanism
- 11:10 Compressive Image Sensor Technique with Sparse Measurement Matrix
- 11:35 Performance Optimization and Power Efficiency in 3D IC with Buffer Insertion Scheme
Industry Forum: Data Analytics and Security in IoT Part I
10:45 - 10:50: Opening by Chair
10:50 - 11:15: Introduction (Sakir Sezer, Queen's University Belfast & CTO
Titan IC, United Kingdom)
11:15 - 12:00: SoC Challenges Enabling Server-based Networking (Ron Swartzentruber, Senior Principal Engineer, Netronome)
Special Session: SoC Architectures for Machine Learning through Inexactness
- 10:45 SoC Architectures for Machine Learning Through Inexactness
- 11:03 CaPSuLe: A Camera-based Positioning System Using Learning
- 11:22 Overcoming the Power Wall by Exploiting Inexactness and Emerging COTS Architectural Features Trading Precision for Improving Application Quality
- 11:41 Low-Power Real-Time Intelligent SoCs for Smart Machines
Thursday, September 8, 12:00 - 13:30
Lunch
Thursday, September 8, 13:30 - 15:10
Advanced SoC Components
- 13:30 Standard Cell Library Based Layout Characterization and Power Analysis for 10nm Gate-All-Around (GAA) Transistors
- 13:55 Comparative Analysis of Hybrid Magnetic Tunnel Junction and CMOS Logic Circuits
- 14:20 Modeling and Simulation of Quantum-Well Infrared Photodetectors
- 14:45 Sensitivity Analysis for SoC Performance Benchmark Against Interconnect Parasitic Resistance and Capacitance Beyond 10-nm FinFET Technology
Industry Forum: Data Analytics and Security in IoT Part II
13:30 - 14:15: Safe Planning and Control Under Uncertainty (Ashish Kapoor, Senior Researcher, Microsoft Research)
14:15 - 15:00: In Silicon We Trust - How to Fix the Internet of Broken Things (Cesare Garlati, Chief Security Strategist, prpl Foundation)
15:00 - 15:10: Interactive session with all the speakers
15:10: Closing by chair
RF, Analog Design II
- 13:30 A Low Power Fourth Order ΣΔ CMOS Modulator with Subthreshold Amplifier
- 13:55 A Novel Design of a Dual Functionality Read-Write Driver for SRAM
- 14:20 Novel Ultra Low Voltage Mobile Compatible RF MEMS Switch for Reconfigurable Microstrip Antenna
Thursday, September 8, 15:10 - 15:30
Coffee Break
Thursday, September 8, 15:30 - 17:00
Panel Discussion: Spreading intelligence across a trillion devices and making the most of it - How pervasive will sensemaking be in IoT, and which applications will take advantage of it?
PANELISTS:
Ron Swartzentruber (Senior Principal Engineer, Netronome)
Lubna Dajani (Chief Strategy Officer, Intercede)
Ram Krishnamurthy (Senior Principal Engineer, Intel)
Mircea Stan (Professor, University of Virginia)
Yong Lian (Professor, York University)
Thursday, September 8, 17:30 - 18:30
Cocktail Reception
Thursday, September 8, 18:30 - 21:00
Conference Banquet
Friday, September 9
Friday, September 9, 07:30 - 08:30
Breakfast
Friday, September 9, 08:30 - 10:10
Intel Training Workshop Part I
This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and performance optimization features that keep the development time short and productivity high.
SoC Design Methods and Algorithms II
- 08:30 Heterogeneous Memory Assembly Exploration Using a Floorplan and Interconnect Aware Framework
- 08:55 Variable-Length VLIW Encoding for Code Size Reduction in Embedded Processors
- 09:20 Self-dual Diamond-graph CMOS H-bridge Logic Family
- 09:45 ERFAN: Efficient Reconfigurable Fault-Tolerant Deflection Routing Algorithm for 3-D Network-on-Chip
Special Session: Emerging Stochastic Computing and Neuromorphic Computing: Arithmetic, Algorithm, and Applications
- 08:30 Design of High-speed Low-power Polar BP Decoder Using Emerging Technologies
- 08:55 A Low-Computation-Complexity, Energy-Efficient, and High-Performance Linear Program Solver Using Memristor Crossbars
- 09:20 Efficient Hardware Architecture of Softmax Layer in Deep Neural Network
- 09:45 Noisy Neuromorphic Circuit Modeling Obsessive Compulsive Disorder
Friday, September 9, 10:10 - 10:30
Coffee Break
Friday, September 9, 10:30 - 12:10
Intel Training Workshop Part II
This hands on workshop will cover the background of how software programmers can use OpenCL to target FPGAs without any former knowledge or experience with FPGAs to build embedded vision applications. We will cover writing OpenCL code and compiling it for an FPGA accelerator, the resulting acceleration system generated, and the mechanisms to run OpenCL kernels on the FPGA while communicating with the host program running on a CPU. Lastly we'll discuss various Altera SDK for OpenCL productivity and performance optimization features that keep the development time short and productivity high.
Low Power Design
- 10:30 Practical Power Consumption Analysis with Current Smartphones
- 10:55 Fully Parallel Content Addressable Memory Design Using Multi-Bank Structure
- 11:20 New Power Budgeting and Thermal Management Scheme for Multi-Core Systems in Dark Silicon
- 11:45 Overoptimistic Voltage Scaling in Pre-Error AVS Systems and Learning-Based Alleviation
Special Session: Security and Validation in Mobile, Embedded, and IoT Systems
- 10:30 Security Challenges in Mobile and IoT Systems
- 10:50 Quantifying Trust in Autonomous System Under Uncertainties
- 11:10 Striking a Balance Between SoC Security and Debug Requirements
- 11:30 Can We Bell the CAD?
- 11:50 Mobile Connected Devices: Security Challenges and Opportunities
Friday, September 9, 12:10 - 13:00
Lunch
Friday, September 9, 13:00 - 17:30
Post Conference Event: The Museum of Flight Tour (not included in registration)
Enjoy the wonder of flight in one of Seattle's most spectacular settings. Walk the aisle of JFK's Air Force One and climb aboard the West Coast's only Concorde. Revel in the history and heroics of WWI and WWII. Barrel-roll a Mustang, land on the moon, and soar over Puget Sound in a simulator. Experience the excitement of the space race and sit at the controls of the world's fastest jet. From the Wright brothers to the exploration of Mars, you'll find it at The Museum of Flight!
This 15-acre campus includes over 160 air and spacecraft, the original Boeing Aircraft factory, flight simulators, and dozens of fun, interactive exhibits and family activities. From the world's oldest fighter plane to the supersonic Concorde, the only full-scale NASA Space Shuttle Trainer and the beautiful Boeing 787 Dreamliner, you'll see the machines and experience the stories of those who flew them. The unique, 3-acre Aviation Pavillion offers the dramatic development of large aircraft in an open-air gallery with a cafe and children's playground.
This tour is not included in your conference registration. Ticket Price: $37 + tax/ticketing fee, includes transportation and admission to the museum.
Program last updated on no date/time given