An FPGA Resource Adaptable General Neural Network Accelerator

Chengsen Dong and Zheng Xie (University of Central Lancashire, United Kingdom (Great Britain))

As Artificial Intelligence is becoming embedded in people's lives; the evolution of Internet of Things is moving towards edge computing where the speed and power consumption of data processing is critical. The feature of re-programmability and power efficiency has powered FPGA as a promising edge processing hardware platform for accelerating deep neural networks. An FPGA resource adaptable neural network accelerator is proposed in this paper. The architecture and behavior of this accelerator is determined only by the way of programming with C language. The design in C code is converted to a description in a form of hardware description languages, VHDL or Verilog. The conversion is taken by a High-Level Synthesis (HLS) software provided by Xilinx Vivado development package. Since the accelerator architecture is fully parameterized in the C code, it can be tailored freely according to the availability of FPGA logic elements, and hence implemented in different types of FPGAs. The proposed accelerator has a configurable register unit, which enable it dynamically change the computing behavior according to the computing requirements of different neural networks without changing the design of architecture.

Journal: International Journal of Simulation- Systems, Science and Technology- IJSSST V23

Published: no date/time given

DOI: 10.5013/IJSSST.a.23.02.05