An Efficient Software Tool Based on SCOAP for Testability Analysis of Combinational Circuits

Sreeja Rajendran (Dhirubhai Ambani Institute of Information and Communication Technology, India); Mary Lourde Regeena (BPDC, Dubai & BPDC, United Arab Emirates)

Identification of regions of a logic circuit which are poorly testable is referred to as Testability Analysis. It is generally computed using either Sandia Controllability Observability Analysis Program (SCOAP) or Probability based Analysis. Logic circuits usually consist of thousands of gates. Software tools which performs the testability analysis of digital circuits will ease the computation process and at the same time provide high degree of accuracy. This paper discusses a software tool developed to compute the testability parameters namely the controllability and observability of each node in the circuit using MATLAB. The developed testability analysis software tool takes Hardware Description Language (HDL) file as input and generates the controllability and observability values of each node described by the HDL. The possibility of utilizing testability analysis for detection of Hardware Trojans (HT) is also discussed in this paper. The effect of HT insertion on a system is evaluated using c-17 benchmark circuit and the results are presented.

Journal: International Journal of Simulation- Systems, Science and Technology- IJSSST V20

Published: Feb 27, 2019

DOI: 10.5013/IJSSST.a.20.01.30