Evaluation of Dual Rail Complete Detection Circuitry Using Asynchronous Delay Insensitive Frameworks

J Sudhakar, Durga A l and Sushma K (Vignan's Institute of Engineering for Women, India)

This paper proposes a testable design of Delay-Insensitive nanoscale framework using different registers such as normal Sleep Convention Logic (SCL) register, modified SCL register and SCL scan cell. Combinational logic blocks in nanoscale frameworks cannot rouse until a complete DATA set is accessible at the input of their preceding register, input-completeness to DATA is also unequivocally ensured. These are characterized in terms of speed and power. Dual rail pipelined versions are developed, and those comparisons are carried out by several parameters mainly focus on power dissipation, delay, slew rate, rise time and fall time.

Journal: International Journal of Simulation: Systems, Science and Technology IJSSST V19

Published: Jun 30, 2018

DOI: 10.5013/IJSSST.a.19.03.10