Performance Explorations of Multi-Core Network on Chip Router
Umathurai Saravanakumar (Muthayammal Engineering College (Autonomous), Rasipuram, TN, India); R Rangarajan (Principal Indus College of Engineering, India)
Due to minimization of communication latency, timing constraints and energy consumption, Network on Chip (NoC) dominated Multi-Core System on Chip (SoC). In order to keep up the balance between power, area, performance and robustness to traffic changes in NoC, many research works conduct by designers. Here, we proposed new router architectures for Multi-Core NoC which gives less slack time than the conventional Wormhole router architecture. Different stages of pipelining method and hierarchical concept in scheduler implemented at the input side of proposed router. The working function of new architecture had verified by simulation and area, power and delay calculated by Synopsys tool in UMC 0.13 µm. FPGAs are identified as an incarnation of NoC, then the proposed architecture implemented in Virtex II Pro. And finally proposed router architecture compared with previous router architectures in terms of power, area and slack time.
Journal: International Journal of Simulation- Systems, Science and Technology- IJSSST V13
Published: Feb 27, 2012