Program for 21th International Conference on Microelectronics (ICM 2009)

Traditional design approaches attempt to guarantee 100% error-free SoCs using a number of fault-tolerant architectural and circuit techniques. However, advanced manufacturing technologies will make it economically impractical to insist on a 100% error-free SoC in terms of area and power. This tutorial addresses this notion of error-awareness across multiple abstraction layers – application, architTo achieve this one must synergistically bring together expertise at each abstraction layer: in communication/multimedia applications, SoC architectural platforms, and advanced circuits/technology, in order to allow effective co-design across these abstraction layers. Earlier versions of this tutorial were successfully presented at VLSI’08, ASP-DAC 08 and DATE 09. All venues were very well attended and feedback indicated that the presentations were well received by the attendees.

Recent years have seen a tremendous growth in the number of research and development groups at universities, research labs, and companies that have started using Boolean Satisfiability (SAT) algorithms for solving different decision and optimization problems in Computer Science and Engineering. This has lead to the development of highly-efficient SAT solvers that have been successfully applied to solve a wide-range of problems in Electronic Design Automation (EDA), Artificial Intelligence (AI), Networking, Fault Tolerance, Security, and Scheduling. Examples of such problems include automatic test pattern generation for stuck-at faults (ATPG), formal verification of hardware and software, circuit delay computation, FPGA routing, power leakage minimization, power estimation, circuit placement, graph coloring, wireless communications, wavelength assignment, university classroom scheduling, and failure diagnosis in wireless sensor networks. SAT solvers have recently been extended to handle Pseudo-Boolean (PB) constraints which are linear inequalities with integer coefficients. This feature allowed SAT solvers to handle optimization problems, as opposed to only decision problems, and to be applied to a variety of new applications. Recent work has also showed that free open source SAT-based PB solvers can compete with the best generic Integer Linear Programming (ILP) commercial solvers such as CPLEX. This tutorial is aimed at introducing the latest advances in SAT technology. Specifically, we describe the simple new input format of SAT solvers and the common SAT algorithms used to solve decision/optimization problems. In addition, we highlight the use of SAT algorithms in solving a variety of EDA decision and optimization problems and compare its performance to generic ILP solvers. This should guide researchers in solving their existing optimization problems using the new SAT technology. Finally, we provide a prospective on future work on SAT.

In the last years, MOS Current-Mode Logic (MCML) circuits have become very popular in a wide range of applications, from high-accuracy mixed-signal circuits to very high-speed circuits, and very recently for ultra-low power circuits. In MCML circuits, desirable features come at the cost of static power consumption, hence power-aware design techniques are needed. At the same time, issues related to the high complexity of current circuits (e.g., design automation) and nanometer technologies (e.g., variability) must be explicitly taken into account in real designs. In this tutorial, a survey of fresh ideas and recent techniques to design MCML circuits is presented. Concepts are introduced in a design perspective and cover multiple levels of abstraction, ranging from transistor to system. A comparison with CMOS logic is presented to identify the applications where MCML exhibit better features. Models for MCML circuits in nanometer CMOS technologies are presented and then used to derive power-aware design guidelines and criteria for a wide variety of applications. Since commercial CAD tools do not explicitly support differential logic styles, issues related to the CAD-based automated design of complex circuits are discussed, and recently proposed solutions are reviewed. Guidelines are developed to design standard cells and perform automated synthesis and place & route with standard tools. Design criteria for area-power efficient differential routing are also given. Variability issues are explicitly dealt with and considered from the beginning, rather than as an afterthought. System-level biasing schemes to dynamically control the power-speed tradeoff and compensate variations are discussed for a wide range of applications, from very high speed to ultra-low power. MCML gates are also shown to be better suited for ultra-low power operation (e.g., to implement the digital processing unit in wireless sensor nodes), compared to CMOS logic. Design issues arising in the ultra-low power realm with a power consumption in the order of pW-per-gate are discussed, and appropriate circuit techniques to allow reliable operation are presented. Limits to ultra-low power operation are analyzed by evaluating the minimum supply voltage that is allowed in MCML circuits, and recent body biasing techniques to push down this voltage limit are discussed. The impact of process/voltage/temperature variations is extensively analyzed to understand the intrinsic advantages of MCML circuits in ultra-low power circuits, and design strategies to counteract power-delay variations are presented. Finally, open questions and aspects that require further investigation are discussed, and new directions for the foreseeable future are proposed.

The successful design of microwave integrated circuits is the fruit of a disciplined design approach. This tutorial covers the theory, and practical strategies required to achieve first-pass design success. Specifically, the workshop covers the monolithic implementation of microwave circuits on substrates such as GaAs or GaN including instruction on simulation, stability analysis, and layout. Numerous design examples are provided.

The evolution of semiconductor industry is allowing heterogeneous system integration, i.e. combining individual electronic components that use different technologies and materials. Integration technologies promise dramatic increases in the functionalities of silicon-based components, whose use then allows for a large cost reduction of the global system. Traditionally, heterogeneous system integration is a multidisciplinary approach, allowing flexible integration of different elements such as Micro-Electro-Mechanical Systems (or MEMS), optoelectronics, active and passive components and bio-electronics into a single package. With the advances of CMOS technologies towards Nanoelectronics, a new paradigm of integrated heterogeneous systems is emerging, based on Nano-Electro-Mechanical Systems, or NEMS.

Hyperbolic sine (Sinh) CMOS filters are of inherent class-AB nature and offer high dynamic range at half the total capacitance value when compared against their pseudo-differential class-AB log-domain counterparts. This characteristic renders their theoretical and practical study valuable. Only a very limited number of CMOS Sinh filter topologies have been reported in the literature to date mostly due to the considerably increased mathematical complexity associated with their design. This paper presents the transistor-level synthesis and investigates in detail the performance of a 3rd-order Sinh CMOS 8Hz low-pass filter of Bessel approximation suitable for ECG processing. The filter is based on recent progress made and has been designed in the commercially available 0.35μm AMS process. Its static power consumption amounts to 0.1μW while its dynamic range exceeds 110dBs. The new filter exhibits a flat group delay of less than 1% error up to 6Hz and good variability performance verified by means of Monte Carlo simulations. The suitability of the filter as part of an ECG front-end is confirmed by the processing of artificially generated ECG signals contaminated by various simulated noise sources and fed as signal inputs into the Cadence Design Framework.

Functional Electrical Stimulation (FES) is an attractive solution to restore some lost or failing physiological functions. Obviously, the FES system may be hazardous for patient and the reliability and dependability of the system must be maximal. Unfortunately, the present context, where the associated systems are more and more complex and their development needs very cross-disciplinary experts, is not favorable to safety. Moreover, the direct adaptation of the existing dependability techniques from domains such as space or automotive is not suitable. Firstly, this paper proposes a strategy for risk management at system level for FES medical implant. The idea is to give a uniform framework where all possible hazards are highlighted and associated consequences are minimized. Then, the paper focuses on one of the most critical part of the FES system: analog micro-circuit which generates the electrical signal to electrode. As this micro-circuit is the closest to the human tissue, any failure might involve very critical consequences for the patient. We propose a concurrent top-down and bottom-up approach where the critical elements are highlighted and an extended risk analysis is performed.

Implantable biomedical devices such as sensors and neurostimulators require a near-field inductive link to transmit power wirelessly. However, the near-field induced voltage is usually much larger than the compliance of low-voltage integrated circuit technologies. Thus most integrated power recovery approaches limit the induced signal to low-voltages with inefficient shunt regulation, or voltage clipping. We propose using a high-voltage (HV) CMOS technology to fully integrate the inductive power recovery front-end while adopting a step-down approach where the induced signal is limited to a much higher voltage (20 V). We previously reported a first IC that includes a HV rectifier and a HV regulator, which provide up to 12 V regulated DC supply from a 20 V maximum AC input. In this paper, we report the design of a second HV custom IC that completes the front-end by integrating an adjustable step-down switched capacitor DC/DC converter (1:3, 1:2 or 2:3 ratio). The IC has been submitted for fabrication in DALSA-C08E technology and the total silicon area including pads is 9mm2. Post-layout simulation results show that the DC/DC converter achieves more than 90 % power efficiency while providing about 3.9 V output with 12 V input, 1 mA load, 1:3 conversion ratio, and 50 kHz switching frequency.

This paper describes and analyzes the optimization of a low-noise and high-bandwidth transimpedance amplifier featuring a large dynamic range. The designed amplifier is configured on three identical stages that use an active load. This topology displays a transimpedance gain of 160 kΩ, which is necessary to obtain a high sensitivity. This structure operates at 3.3V power supply voltage, exhibits a gain bandwidth product of 28 THzΩ and a low-noise level of about 0.862 pA/Hz0.5 This transimpedance amplifier can reach a transmission speed of 350 Mb/s for a photocurrent of 0.5 μA. The predicted performance is verified using simulations by means of PSPICE with 0.35 μm CMOS AMS parameters.

a high selectivity switched capacitor (SC) bandpass filter is introduced in this paper which is derived from Fleischer and Laker SC biquad [7]. High quality factors are obtained by means of a proposed Q-factor tuning technique that is applied by changing the effective sampling frequency of the clock signals of a positive feedback switched capacitor branch. The center frequency is 17.4 KHz and Q-factor ranges from 0.53-27.04. Spice simulations are provided for the filters. Active blocks are used to realize SC filters where an Operational Amplifier is used for simulation.

In this paper a sixth order programmable low pass filter has been realized using 0.25μm CMOS technology model. The filter is based upon Active-Gm-RC structure. The proposed programmable LPF is realized using Variable Gm-Cc OP-AMP with a tunable unity gain frequency ranges from 297KHz to 41.7MHz and compared to the proposal in [1]. The filter is based on cascading bi-quadratic Active-Gm-RC cells. The filter operates from single supply of +1.7V. Simulations results using PSPICE for the proposed programmable LPF are presented in this paper. Comparisons are included to view the points of strength for the proposed architecture. The simulation results were found to be in good agreement with theoretical expectations.

This paper addresses the analysis of three different fourth order low pass filters at cutoff frequency of 10MHz. The filters are realized using: the inverse follows the leader feedback (IFLF), the leap frog (LF), and cascaded Multiple loop feedback (MLF) OTA-C filters, with voltage and current transfer functions. A CMOS operational transconductor amplifier (OTA) cell proposed in [1] is used to realize the three filters. PSPICE simulations are done using 0.25μm model and supply voltage of ±2.5V. A comparison between the different filters proved that the current transfer function filters have a lower cutoff frequency error between the theoretical and simulation values, and a lower output referred noise density under 1KΩ load by a factor of 10-3. The voltage transfer function has the advantage of having a lower group delay than that of the current transfer function filters.

This paper investigates the impact of device scaling on the bulk-driven MOSFET. In particular, the behavior of gmb is observed across process technology and it is shown that the gmb/gm ratio falls from 0.38 to 0.12 between IBM’s 0.25 μm and 65 nm bulk CMOS processes via simulation. Delta and step doping are then proposed to enable the scaling of bulk-driven MOSFETs down to a channel length of 80 nm on a one volt supply. Using 2-D device simulations in ATLAS, it is shown that the intrinsic gain of a bulk-driven MOSFET can be enhanced by as much as 78% for a step doping profile and 106% for a delta doping profile in an NMOS device when compared to a uniform substrate.

In this paper, attacks aiming at recovering the secret key of a cryptographic core from measurements of its static (leakage) power are presented. These attacks exploit the dependence of the leakage current of CMOS Integrated Circuits (ICs) on their inputs (e.g., the secret key of a cryptographic circuit). For this reason, these novel attacks are referred to as Leakage Power Analysis (LPA) attacks in this paper. Since the leakage power increases much faster than the dynamic power at each new technology node, LPA attacks are shown to be a serious threat to information security of cryptographic circuits in sub-100 nm technologies. For the first time in the literature, a well-defined procedure to perform LPA attacks is presented. Advantages and measurement issues are also analyzed in comparison with traditional Power Analysis attacks based on dynamic power measurements. An experimental attack to a register is finally performed for the first time.

Adaptive filtering is used in a wide range of applications including echo cancellation, noise cancellation and equalization. In these applications, the environment in which the adaptive filter operates is often non-stationary. For satisfactory performance under non-stationary conditions, an adaptive filtering is required to follow the statistical variations of the environment. Tracking analysis provides insight into the ability of an adaptive filtering algorithm to track the changes in surrounding environment. The tracking behavior of an algorithm is quite different from its convergences behavior. While convergence is a transient phenomenon, tracking is a steady-state phenomenon. Over the last decade a class of equivalent algorithms such as the Normalized Least Mean Squares algorithm (NLMS) and the Fast Recursive Least Squares algorithm (FRLS) has been developed to accelerate the convergence speed. In this paper, we introduce an improved version for the stabilized Fast Recursive Least Squares (FRLS) algorithm. A comparative study between the Normalized Least Mean Squares algorithm and the Fast Recursive Least Squares algorithm is also presented in context of tracking systems identification.

This paper presents a low noise, low offset and wide dynamic range Hall effect magnetometer integrated in a 0.35 µm CMOS technology. It features a spinning-current operated Hall device and a chopper stabilization, which has been unconventionally implemented using high-pass filters. The magnetometer exhibits 350 µT offset, can measure magnetic fields up to 1T with 10 µT resolution over a 3.6 kHz bandwidth.

the paper presents the design of readout circuits for signal processing of an in-vivo dosimeter. The circuit includes a photodiode and highly sensitive charge amplifier. The readout configuration is mainly based on the use of the correlated double sampling (CDS) technique and series reset of integration capacitor to allow the optimization of the noise performance and sub-pA level resolution.

This paper describes the HW/SW development of a SoC platform for Voice over Internet (VoIP). To build the platform, we have adopted the OpenCores-Opensources design concept. The platform includes a software part and a hardware part. The software part is related to the VoIP application configuration. The hardware part is represented by the VoIP gateway architecture , which is mainly based on the OR1200 processor , some basic peripherals, such as debug interface for debugging purpose, a Direct Memory Access (DMA), a Memory controller two external Flash and SDRAM memories, an Universal Asynchronous Receiver Transmitter (UART), an Audio codec for voice coding, a standard 10/100 MAC/Ethernet for network interface and an internal boot memory. The cores are connected through the WISHBONE bus interface. The platform uses a set of tools including a compiler, assembler, debugger that is built for system debugging and software development. The benefit of using the Opencores/ Opensources methodology is flexibility, reuse and accessibility of the cores at free cost. The design is done using Verilog language. The architecture is built in selected technological target Virtex- II XC2V3000 FPGA development board. The gateway architecture occupies 40% of logic resources and 22 % of IOBs. In software part, we have tested an embedded network application which is the main step in a VoIP application, using uClinux as an operating system and the 10/100 MAC/Ethernet as a network controller.

This paper deals with the design of a processor for very-finely spaced spectral analysis over a narrow band of the available spectrum. The processor implements the chirp z-transform (CZT) algorithm, and exploits a fully-parallel architecture in order to address real-time applications with very-high throughput. The internal data-path is optimized as a trade-off between fixed-point accuracy and implementation complexity. The proposed architecture has been customized for the case study of a 64-point transform in a sub-band of 10% of the available spectrum, and has reached the astonishing throughput of 3.2Gs/s on a Xilinx Virtex-IV FPGA. Also, compared with a customary approach based on FFT, a remarkable saving in complexity is shown.

This research paper models the Kerwin Huelsman Newcomb (KHN) band pass filter [1] using standard hardware description language (VHDL). The illustrated modeling approach allows simulating analog building blocks using a language used for describing digital hardware. Simulation results using the proposed VHDL model of the KHN filter for both in time and frequency are given. PSPICE simulation results confirm the VHDL simulation result are also given.

In this paper, we propose an efficient 8×8 transform matrix for image compression by appropriately introducing some zeros in the 8×8 signed DCT matrix. We show that the proposed transform is orthogonal, which is a highly desirable property. In order to make this novel transform more attractive for recent real-time applications, we develop an efficient algorithm for its fast computation. By using this algorithm, the proposed transform requires only 18 additions to transform an 8-point sequence. Compared to the existing 8×8 approximated DCT matrices, it is shown that savings of 25% in the number of arithmetic operations can easily be achieved using the proposed transform operator without noticeable degradations in the reconstructed images. We also present simulations on some standard test images to show the efficiency of the proposed transform in image compression.

In this paper, a novel empirical-analytical study is performed on the design of low power and robust continuous time Sigma-Delta modulators. The proposed method makes the modulators more stable against the excess loop delay of the feedback loop. Besides; it enforces easy constraints on integrators of the modulator so that we can realize the integrators with a unity gain bandwidth identical to the sampling frequency of the modulator. In order to design a more stable NTF, this method employs both the phase margin (PM) and gain margin (GM) stability criteria.

Nonlinearity is one of the phenomena that affect the ultrasonic wave during its propagation in a given medium. In the time domain the nonlinearity is seen as a variation of the phase velocity which leads to a distortion of the wave form that corresponds in the frequency domain to energy transfer from the fundamental frequency to the harmonic and among the harmonic themselves. Our previous work was axed on the modelling with the simulation tool PSpice of the absorption and the diffraction effects on the wave propagation. The aim of this paper is to introduce the PSpice implementation of the computational model of the nonlinear ultrasound propagation. We study first the plane wave distortion based on the Burgers' equation. Our PSpice model allowed studying the temporal profile of the ultrasonic wave during its propagation. The simulation results are compared to the analytical solution of the burgers' equation showing the validity of the model.

A voltage-mode multiphase oscillator topology is introduced in this paper. It is realized by employing Current Feedback Operational Amplifiers and only grounded passive elements. Compared with the corresponding already known topology, the offered benefits are the capability for obtaining both odd and even number of phases without modifying the core of the topology and the absence of employment of the CFOA parasitic poles. The behaviour of the proposed topology has been evaluated through experimental results, by utilizing the AD844 discrete CFOA component.

This paper describes the operation theory, mathematical analysis and simulation of parallel summation type of the true piecewise approximation logarithmic amplifiers. It also reports a programmable logarithmic amplifier to have a desired logarithmic characteristic in special applications. To design the programmable structure, mathematical analysis of parallel summation type of the true piecewise approximation logarithmic amplifier is performed and based on it, a new method for improving its characteristic and some methods for adding flexibility and programmability to the structure is described. The presented programmable logarithmic architecture can be used in applications with variant and uncertain input signal range such as wide range wireless receivers and radar applications.

This paper describes the per-pixel readout circuit of an imaging matrix and compares it with other solutions. The per-pixel readout circuit consists in a digital pixel sensor array constituted by a photodiode and a one-bit first-order sigma-delta analog to digital converter for each pixel. The output of each pixel is a digital bit stream, containing information about the intensity of the light that falls into its photodiode. The sigma-delta A/D converters use only ten small size MOSFETs and one capacitor. The comparison between the solution presented here and other solutions show that the circuit complexity is similar but the performance, in terms of signal to noise ratio, is superior.

In conventional cmos charge pump circuits, there are some non-ideal effects such as the clock feed through, current mismatch and charge sharing which result in a phase offset in phase-locked loop circuits. This paper presents a new charge pump to reduce the phase noise. The proposed and conventional charge pumps are simulated and compared. The circuit is implemented using a 0.35µm mix-signal CMOS process. And the simulation result is obtained by SPECTRES

Continuous-time (CT) quadrature bandpass (QBP) delta-sigma (ΔΣ) modulator is already in itself a mixed-signal system. That fact creates a discontinuity in the traditional IC design flow which assumes that “discrete” and “continuous” time domain designs require separate design tools. This paper presents an efficient top-down methodology for mixed-signal design. We report the design process from the system-level down to gate/transistor-level; modeling and simulation are applied to the ΔΣ modulator. We have verified the robustness and effectiveness of our approach which resulted in shorter design process cycles and higher rates of success.

In this paper, the layout density of FinFET logic gates is analyzed and compared to that of bulk CMOS logic. Analysis starts from basic structures, including single- and multi-finger transistors, as well as stacked transistors. As opposite to previous work, four-terminal (4T) FinFETs are also explicitly taken into account. The analysis is extended to the physical design of a standard cell library in 65-nm technology. Comparison with bulk technology confirms that 3T FinFETs suffer from significant layout density degradation, as was previously observed in [1]. Moreover, it is shown that 4T FinFETs have a considerably worse layout density, compared to 3T FinFETs and bulk transistors. The sources of the 3T-4T layout density degradation are also discussed. Finally, the mixed 3T-4T approach, which was recently proposed to reduce the leakage power, is investigated as a compromise between 3T and 4T FinFET circuits in terms of area.

In this paper, the impact of the clock slope on the performance of high-speed Differential flip-flops in a 65-nm CMOS technology is discussed. Usually the local network that distributes the clock signal to the flip-flops is designed to guarantee a steep clock waveform in order to not compromise the flip-flops performance. We show that, even doubling the clock slope (or more) with respect to typical FO2÷FO3 values, the impact on the Differential flip-flops speed is negligible. Correspondently, their energy dissipation increases but this drawback is balanced by the lower consumption resulting from the local clock distribution buffers, whose size/number can be reduced. Therefore, a tradeoff arises and, on the whole, the optimum clock slope can be different from the usual FO2÷FO3 assumption. This result allows to relax the local (domain) clock network design, thereby reducing the energy consumption associated with the distribution of the clock within a domain. Results with a 65-nm technology show that the resulting energy saving can be up to 60 %.

This paper addresses a transistor level design for manufacturing methodology. Design efforts are devoted to robustness against process variations. Temperature and voltage tolerances should also be tackled for mass production. A structured design methodology contemplating issues like intuitive design and Monte-Carlo simulations is proposed. As an illustrative example, the methodology is applied to the design of a Cellular Non-linear Network cell in UMC 130nm CMOS technology.

Recent FPGA architectures facilitate the efficient mapping of high order compressors to implement multi-operand additions. This feature can be used to improve the performance and area utilization of large size multipliers. In this paper we present an improved design approach utilizing ternary adders and Generalized Parallel Compressors, GPCs, for the addition of the partial products. Multipliers of different sizes ranging from 80 bits to 170 bits were implemented on Altera’s Stratix III devices. The results of our proposed scheme are compared to the standard ripple-adder-based multipliers. On average, a delay reduction of 17.7% and area saving of 56.53% were achieved when using ternary adders. Using the GPCs with one level ternary adder, the average delay reduction is 18.7% and the average area saving is 24.1%.

As the semiconductor process technology continues to scale deeper into the nanometer region, the intrinsic parameter fluctuations will aggressively affect the performance and reliability of future microprocessors and System-on-Chip (SoC) applications. These system requires large SRAM arrays that occupy an increasing fraction of the chip real estate. To investigate the impact of process fluctuation, specifically intrinsic parameter fluctuation (IPF) from systems point of view, a framework to bridge architecture-level and device-level simulation will be utilized for data cache built from transistors with 25 nm, 18 nm and 13 nm technology node. This study found that the IPF will not have any significant impacts on data cache memory systems build with 25nm while increasing the memory cell ratio to two will overcome the IPF impacts for the 18nm. However, the 13 nm technology data cache could not operate even with higher cell ratio. Common, cache memory fault detection and correction such as ECC and redundancy can only partially remove the fault due to these process fluctuation.

As India is making rapid progress in terms of GDP growth, two distinct Indias are emerging. The first one, India-1, is the upper middle class whose technology consumption is similar to ‘globals’. These users are just as sophisticated as the users in the rest of the mature markets and do not require and localization or customization for product penetration in the local markets. The second group, India-2, is represented by value conscious lower middle class ‘aspirers’. Affordability and desirability become most influencing consumption factors and bringing technology to these consumers. India is seeing a rapid growth in the mobile market as well as Internet access and there is national consensus on the economic impact of broadband today. The objective of this product initiative from Intel India is to address cost and connectivity factors and to bridge the gap in the “digital divide” by providing means and access to information and knowledge in India-2. It is estimated that WiMAX subs will grow in India to 19M by 2012.

With the Healthcare Delivery Systems being overloaded in the developing and densely populated countries, such as India and China, it is imperative to have efficient and cost-effective systems and processes. Building fresh leadership acumen in a complex and changing environment, establishing organizational excellence and designing new service delivery models will help us face the challenges. Building better forward and backward linkages through a superior referral system would cause the secondary and tertiary care facilities to become more manageable, preventing them from being over burdened. Use of Information Technology in Healthcare, especially a Unified Healthcare Management Solution, can potentially improve healthcare. Kshema offers medical diagnosis, ongoing patient care and has an ability to monitor patients remotely by using innovative applications with the underlying cost-effective technologies. Kshema unifies diagnostic hardware like Microscope, Vital Signs Monitor, ECG machine with the diagnostic software. The software consists of modules for Electronic Health Records, Pathology, Radiology and Vital Signs. The software has the ability to automatically identify the vital parameters and transmit the parameters to the remote doctor through broadband or wireless connectivity. Kshema offers simplicity and cost efficiency making it an ideal solution for use in rural areas where efficiency of healthcare delivery systems is critical. Currently Kshema is being used at four primary healthcare centers in Karnataka, India and the results are very encouraging.

The mounting pressures on conventional energy sources and recent findings on climate change have brought attention to not just how we use energy but also how we manage it and ultimately how we conserve it. Rapid urbanization and increased infrastructure development have posed challenges on how to improve the quality of life without compromising the environment. Cities, today, consume 75% of the world’s energy and worldwide consumer electronics represent 15% of the household power consumption. Intelligent and automated solutions are required to enable the consumers to not only measure how energy is used but also to monitor and manage it. Studies have shown that the display of real time information on energy usage, water consumption and carbon dioxide emissions results in a reduction of nearly 15%. This presentation details how open and internet enabled technologies and solutions can enable industries, commercial buildings and private homes to monitor and manage their resource utilization. The solutions focus on ease of use, interoperability and affordability. By integrating with other sensors and systems the solution enables the end user to consume responsibly and manage effectively.

iMFAST, Integra’s award winning innovation was conceptualized, developed by Mr. Pratap. iMFAST is an end – to – end solution for enabling branchless banking, especially at the rural areas of the country. The concept has been widely appreciated by Former president APJ Abdul Kalam, Home Minister P Chidambaram, Dr C Rangarajan, Mr. V Liladhar and Mrs. Usha Thorat, Deputy Governors RBI and CMDs of several banks. Various State Governors, Chief Ministers and other officials have seen and liked the device. This innovation is currently being used by 13 national banks all over the country. This paper will talk about bringing HW and SW technology to bring common man participate into the economic growth of the country. This would describe the current product, its current applications and possible future versions and the applications.

Handheld portable computing is a key enabler for delivery of core services to a wider spectrum of the population in developing countries. This overview paper presents the ProcSys ION, a hand held device developed by Processor System India. The device is based on the Intel Atom processor and is targeted at facilitating inclusive growth in India and other developing markets.The paper outlines the unique requirements called for in these emerging markets, to widen the spread of delivery of financial, health care, public distribution and other core services. The paper also describes how the Intel Atom processor has been leveraged in the ION hand held device to meet these requirements.

This talk is about Challenges and Solutions in Nanoscale Lithography

Discussion of 8500 Single Chip Digital Baseband and Application Processor Architecture and Characteristics

The MoVES framework is being developed to assist in the early phases of embedded systems design. A system is modelled as an application running on an execution platform. The application is modelled through the individual tasks, and the execution platform is modelled through the processing elements, including the operating systems, and their interconnections. The tasks and processing elements are characterized by their real-time properties. The framework can be used to conduct schedulability analysis and has the potential to reason about different types of resource usage such as memory usage and power consumption. A simple specification language for embedded systems and a verification backend are presented. The framework has a modular, parameterized structure supporting easy extension and adaptation of the specification language as well as of the verification backend. We show, using a number of small examples, how MoVES can be used to model and analyze embedded systems.

Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.

The increasing popularity of multi-core System-on-Chip platforms introduces new challenges, both in terms of hardware platforms and design methodologies. Dynamic reconfiguration can be exploited to increase the flexibility of the system and to implement multiple applications, since it is possible to easily switch between them by reconfiguring part of the device at run-time. Additionally, new applications may be included in the system after the design time synthesis has been completed. This paper addresses the problem of mapping new applications on the device area at run-time, by reusing existing components of the system. We propose an heuristic technique that is able to determine how the new application should be mapped in a short time and, thanks to the reuse policy, to immediately deploy the solution on the device. The proposed algorithm also takes into consideration two conflicting performance metrics, in order to generate a good quality result.

In this work, we begin by presenting some of the challenges in the design of heterogeneous multi-physics systems. To address this complexity a methodology based on hierarchical partitioning and multilevel optimization is described. Our implementation, in the form of the design platform RUNE is applied to demonstrate the proposed methodology, and we end the talk by outlining our vision for its application to systems based on heterogeneous 3D integration.

In this paper, novel circuit techniques are proposed to enhance the resistance of precharged busses against Power Analysis attacks. Indeed, a low-power low-area bus coding scheme is used to make power consumption nominally constant. In addition, a simple scrambling technique is developed in order to make the bus robust against attacks even in the presence of process variations or load unbalance. The proposed techniques are shown to be more efficient than the traditional dual-rail pre-charged busses, both in terms of area and power consumption. Measurements confirm that the proposed technique increases the robustness of precharged.

The system-level modeling and simulation framework Sesame/Artemis aims to efficiently explore the design space of heterogeneous embedded multimedia architectures. The Sesame environment provides several methods and tools to quickly and separately build the application process network model, the target architecture model, and the mapping model of the application onto the architecture. In addition, this tool is designed to allow the refining simulation models smoothly across different abstraction levels and to include support for refining only parts of an architecture model, creating a mixed-level simulation model. In this paper, the Sesame software framework is selected to implement at the black-box architecture model level of a parallel H.264/AVC video encoding application targeting multiprocessors platforms.

New standards in communication, multimedia and signal processing have challenged the researchers to formalize the design methodology of an optimized Application Specific Processor (ASP) where the performance requirement should meet operational constraints like speed, chip area and power consumption. In this paper we describe a novel design approach to design a hardware efficient speed optimized power stringent application specific processor customized for a desired high performance. We initiate the design approach with the mathematical model of the application with strict operating constraints as specifications and finally describe the design at register transfer level. The proposed approach is capable for designing an ASP which is efficient not only in terms of hardware area but also contradictory parameters like speed and power consumption. To demonstrate the design approach for this power limited speed optimized ASP we selected digital IIR second order chebyshev filter as the benchmark.

Multicast switches have become indispensible for modern computer networks due to the proliferation of multicast traffic on the Internet. One important issue which greatly affects the performance of a multicast switch is how to reduce data loss caused by blocking during the process of duplication and routing of the packets. In this paper, we propose a multicast crossbar switch with an inner queue at each cross point. With the proposed architecture, no additional control circuits are needed in order to perform duplication and self-routing. To reduce the data loss rate, we store the duplicated packets in the inner queues and wait for the next time slot to proceed. By controlling the interarrival time of two sequential groups of packets, our approach is able to reduce the data loss rate to 10-6 or less. Due to the simplicity of the proposed architecture, hardware implementation can be realized easily with good scalability and stackability. The multicast switch has been implemented and verified on the Altera Stratix II EP2S60F1020 chip. It operates at a clock rate of 80 MHz and uses only eight percent of the available look up tables.

In this paper, we implement and evaluate a novel design for the hardware of the multi-mode interleaver block used in the OFDMA mode of the IEEE 802.16e (Mobile WiMAX) standard. A new architecture that is both area and delay efficient is introduced. The area and delay efficiency of this new architecture is verified via quantitative comparisons between FPGA implementations of this architecture and classical interleaver designs.

This paper proposes different baseband chain architectures used in multi-standard reconfigurable receivers. The architectures are simulated using CMOS 0.25μm technology operating with 1.2V supply voltage. Performance comparisons between different architectures demonstrate the optimum baseband requirements for a multi-standard receiver in terms of DC-Gain, noise, linearity, SFDR, and power consumption.

A wide range Ring VCO operating in the range 1-10 GHz is proposed. The design uses a modified delay cell architecture optimized to work on a wide frequency range. The VCO is designed on a 90 nm technology, consumes around 5 mW of power from a 1 V supply and takes an area of 18.5μ × 35μ.

This paper presents the design of a 10-Gb/s decision feedback equalizer (DFE) or chip-to-chip communications in 90-nm CMOS technology. A fast slicer architecture is proposed that achieves timing constraints without the use of speculation techniques. Removing speculation improves power consumption by 60%. The 5-tap topology was found optimum to compensate for channel losses up to 22 dB. A half-rate architecture is used to enable operation at 10-Gb/s. The DFE system consumes 43 mW from a 1.2 V supply, and occupies an area of 177um * 146um. Post-layout simulations done using a channel with 22dB loss at 5 GHz, demonstrate the effectiveness of the DFE equalization.

This paper presents a detailed system design of PLL frequency synthesizer. The PLL is designed for 2.4 GHz IEEE 802.15.4 Zigbee transceiver (ISM band). The PLL system analysis is meant for Zero-IF transceiver. Hand calculations and assumptions are discussed then validated by ADS system simulations.

A simple new phase frequency detector design is presented in this paper. Falling-Edge PFD uses only 12 transistors and preserves the main characteristics of the conventional PFD. It is implemented using Silterra 0.18μm CMOS Process. It consumes 6.6μW when operating at 50 MHz clock frequency with 1.8V voltage supply. It has free dead zone and operates up to 2.5 GHz. It can be used in high speed and low power consumption applications. A single ended switch at source charge pump is presented as well. It is compatible with the FE-PFD outputs characteristics.

We report on the design and implementation of a fluorescence measurement and analysis device that can identify fluorophore substances. The device performs multi-spectral fluorescence measurements, obtained by exciting the unknown substance with light emitting diodes (LED) whose intensity is CDMA coded for noise rejection. The acquired fluorescence data are processed by a CDMA receiver and a neural network for spectral signature identification and measurement. The design’s front end exploits the capability of color LEDs to act as photodetectors with different spectral responses when reverse-biased. The system avoids using optical lenses and is implemented as a minimum chip count design where an FPGA performs all of the required processing with the exception of the analog front end. It is thus appropriate for field use.

The NTRU encryption algorithm, also known as NTRUEncrypt, is a parameterized family of lattice-based public key cryptosystems. Both the encryption and decryption operations in NTRU are based on simple polynomial multiplication which makes it very fast compared to other alternatives such as RSA, and elliptic-curve systems, especially in resource constrained environments. Recently, the NTRU system has been accepted to the IEEE P1363 standards under the specifications for lattice-based public-key cryptography (IEEE P1363.1). In this paper, we investigate several hardware implementation options for the NTRU encryption algorithm. In particular, by utilizing the statistical properties of the distance between the nonzero elements in the polynomials involved in the encryption and decryption operations, we present different architectures that offer different area-speed trade-off and analyze their performance. A prototype for the proposed design is implemented using virtex- E xcv1600e-8-fg860 FPGA chip.

This paper presents a sequential architecture of a pipelined LMS-based adaptive noise cancellation to remove the power-line interference (50/60 Hz) from electrocardiogram (ECG). This architecture is implemented on on FPGA using XUP Virtex-II Pro development board and Xilinx System Generator (XSG). The proposed architecture was evaluated using real ECG signals from the MIT-BIH database. Hardware requirement of this adaptive noise canceller is presented for various filter lengths.

Fault analysis attacks are powerful cryptanalytic tools that are applicable to many types of cryptosystems. Inducing multiple transient faults and observing the output of the faulty cryptographic device may allow the attacker to collect sufficient information for extracting secret keys and even using the device after breaking the cipher. In this paper, we investigate several options for fault analysis resistant FPGA implementations of the Advanced Encryption Standard (AES), which has become the default choice for various security services in many applications since its adaption as a new encryption standard by NIST. In particular, we compare the throughput and area overheads associated with parity based error detection and (algorithm level, round level and operation level) redundancy based countermeasures. Our comparison also include implementations that already employ some additional countermeasures against power analysis attacks.

MPSOC integrated a variety of heterogeneous components which require a communication between them. A solution to flexibility and reconfigurability of interconnects is the use of Network on Chip (NoC). These latter are likely proposing efficient solutions with the complex problems of the embedded system integrations. Multistage interconnection networks have been frequently proposed as connection means in classical multiprocessor systems. They are generally accepted concepts as on-chip communication platform. We describe in this paper the design methodology and the implementation of a Delta multistage interconnection network on chip. Also, we propose a flexible and an efficient model of MPSOC architecture based on Delta MIN. Finally, the effectiveness of the proposed design methodology is shown through parallelized applications on MPSoC architecture.

We report on the design of a silicon-based 2D slab photonic crystal that operates around telecommunication wavelength (1550 nm). The design uses a honeycomb lattice and achieves a complete photonic bandgap (PBG) for transverse-magnetic (TM) polarized light while preserving a connected pattern for efficient electrical injection. The device operation is based on a dynamic shift of the complete photonic band-gap (PBG) due to induced change in the silicon refractive index by free carrier injection. The plane-wave expansion (PWE) method is utilized to design a honeycomb-lattice line defect photonic crystal waveguide with complete TM PBG. The light modulation performance of the device is simulated using the finite-difference time-domain (FDTD) method. With small size, rapid response time and high extinction ratio, the proposed optical modulator can be easily implemented to design ultra-compact all optical integrated circuits.

In this paper we have proposed a new and more accurate macro-model for simulation of single electron transistors (SETs). Furthermore, this model includes the ability of electron tunneling time calculation. In our proposed model, we have modified the previous models and applied some basic corrections to their formulas. In addition to achievement of more accuracy, we have added a switched capacitor circuit, as a quantizer, to evaluate the time of electron tunneling through the barrier. We used HSPICE for high-speed simulation and observed that our macro-model gives more accurate results than of the other models when compare with SIMON 2.0. This model is completely applicable for calculating the delay time of complicated circuits. *Corresponding Author: Mohammad Reza Karimian Ph.D. Candidate E-mail: mr_karimian2002@yahoo.com & Karimian@iaun.ac.ir

A new method is developed in this work, to seek precise and simple electric models of physical samples. This technique is based on the decomposition of the electric impedance in a series of the elementary electrical circuits. Algorithm and software programs are developed to estimate the order and the number of these basic circuits. Tests are applied on a BST ceramics and Schottky junction. The founding electric models are compared with other models, often used in the literature. Interesting results are observed on the level of the statistical errors and the various significant elements of the models.

An innovative method of device characterization is experimented to qualify annealing Gamma-ray damage in power MOSFETs. The degradation of structural parameters of the body-drain junction for a dose rate of 103.8 rad.mn-1 is presented. Temperature anneal effects, at 100°C, are discussed and analyzed against the evolution of the density trapped oxide and interface charges.

In the present study, we determine exact analytical expression of the current flow through a Schottky barrier diode as a function of the input voltage. The Schottky diode is modeled by an electronic circuit containing four physical parameters: a series resistance Rs, a shunt resistance Rsh, a Schottky diode reverse saturation current Is and a Schottky diode ideality factor eta. Firstly, we solve the characteristic equation and determine the analytical expression of the input current I as a function of the input voltage V of the Schottky diode using the LambertW Function. Secondly, We present two different methods to extract the four physical parameters appearing in the electronic circuit. These methods are applied for two junctions: Iridium-Silicon Carbide Schottky barrier diode at 200K and Gold-Gallium Arsenide at 300K. Finally, we compare the results obtained via the two methods presented.

A new and efficient heuristic methodology, called Full-and- Elimination (FAE), is proposed to solve the floorplan area minimization problem. This approach is inspired by the game, Tetrisr. The modules are selected one at a time and placed to the partial floorplan, while attempting to grow on upper, in a row-by-row manner, until all the modules are arranged to the floorplan. In each row, modules are tried to be placed without deadspace. If any row is filled up, this row is viewed as “full” and thus it is “eliminated”. The modules are sorted and constructively moved into the partial floorplan. A contour that encloses the top of the packed modules in the floorplan is constructed to help for arrangement of the modules. Experimental results on MCNC and GSRC benchmarks demonstrate that we obtain significant improvements on the area minimization and computational efforts. Particularly, our methodology provides greater improvement over other floorplanners as the number of modules increases, which is a feature of scalability.

Abstract—Embedded coarse-grained blocks are becoming increasingly popular in advanced field programmable gate arrays (FPGAs) devices to improve their performance. In this paper a Tree-based coarse-grained FPGA architecture is proposed and it is then compared with VPR-style [1] Mesh-based coarse-grained architecture. Tree-based architecture is a multilevel hierarchical architecture that comprises two unidirectional interconnects whereas Mesh-based architecture is column based that uses unidirectional routing. Both architectures can support different kinds of coarse-grained blocks that are defined using architecture description files. For the evaluation of two architectures, separate software flows are developed for both the architectures that have resulted in the successful placement and routing of various digital signal processing (DSP) benchmarks. Area comparison, based on the results obtained after the placement and routing of these DSP benchmarks, reveals an average area gain of 27% for Tree-based architecture over Mesh-based architecture.

Recently, FPGAs have been integrated into HPC clusters in order to boost their computational performance while reducing the power consumption significantly. However, performance and effective logic utilisation is usually limited by the number of inter-device pins and most importantly the interconnection architecture. Mesh interconnection in particular suffers from the pin-limitation problem. The concept of Virtual Wires has been proposed to reduce the impact of this problem by using time-multiplexed physical wires. This paper demonstrates a simple yet effective technique to further reduce the number of the physical wires required by the Virtual Wires and the Mesh architectures by an average of 18 % over the original routing algorithms. The results found are the same or very closed to the optimum solutions. This technique can be equally applied to exploit the topological properties of any mesh-based architecture.

With the increasing hardware capacity, embedded systems are becoming more and more complex, requiring new design techniques/methods. UML allows higher abstraction level system modeling and MDA techniques allow automatic code generation. In this paper we propose a UML/MDA approach to rapidly model and automatically generate MPSoPC systems. Our approach uses MARTE as extension mechanism in order to allow real-time and platform embedded systems modeling. Our goal is to provide an unique model for MPSoPC co-design, closing the gap between hardware and software modeling. Also, we propose an efficient method for IP (Intellectual Property) reuse allowing automatically platform code generation. Our tests have shown gains in the order of 30% in design time.

Multiway Decision Graphs (MDGs) are special decision diagrams that subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of datapath circuits. In this paper we propose a new specification language, Abstract Property Language (APL), for the MDG model-checker. The APL language eradicates the restrictions present in the existing Lmdg specification language and introduces new operators to improve expressiveness. The paper also presents the design of a front-end translator that accepts specification in APL and builds composite MDG model with the specification directly embedded into its MDG-HDL representation. Finally, some experimental results are presented to show the performance of the APL-Tool and the analysis of the generated code executed on benchmark properties.

Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reconfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

In this paper, we propose a new scheme of Hybrid ARQ strategy, based on Blind Separation Sources over Multi Input Multi Output (MIMO) architecture. In the classical HARQ case, when the received packet is erroneous, the system should send a NACK to ask the transmitter to re-send the same packet. Known that in this case, the receiver could use different copies of the emitted signal to ensure a combination of ARQ, we propose in our approach to transmit different copies of the same packet, but simultaneously over multiple antennas, in order to provide a MIMO system. This approach makes possible the recovering of the erroneous packets, by using the received copies instead of asking for a retransmission, which is very time- and treatment- consuming. The temporary diversity is assured by applying the interleaver to each copy of the transmitted packet, as well as the determination of the emitted signal's copies by using the Blind Separation Sources (BSS) concepts, without prior information about the transmission channel. The simulations show that the proposed scheme provides good results in term of frame error rate.

Software-Defined Radio (SDR) is a rapidly evolving Technology. SDR have been widely studied as a solution to support multiple competing and in compatible air interface standard in future wireless communications. In this paper, we present the design of a Digital Down Converter (DDC) module for triple-mode WCDMA, CDMA2000 and GSM. The designed module consists of digital mixer, CIC filter, and decimation filter and frequency converter. Theses sub-modules are software reconfigured in architecture to be compatible with WCDMA, CDMA2000 and GSM. The design is software configured with minimum hardware and maximum operating speed.

This paper presents single amplifier biquads and active-gm-RC cells with programmable unity gain frequency operational amplifiers. A complete baseband chain for Software- Defined Radio is designed using these building blocks. The baseband chain consists of a reconfigurable low pass filter and a variable gain amplifier. The LPF is a sixth order filter with cut off frequency range from 380 kHz to 33.4 MHz. The VGA is made up of two cascaded gain stages. The baseband chain is realized in 0.25
m CMOS technology with 1.2-V supply voltage. PSPICE simulations are presented.

In this paper, we present an FPGA implementation of an improved channel estimation technique for the OFDM based WiMAX systems. The proposed technique is a modified version of the well-known MMSE technique. The implementation minimizes the complexity of the accurate MMSE based channel estimator by making use of sets of previously calculated filter coefficients in estimation. The hardware architecture presented has a major advantage which is its ability to adapt itself to cope with different wireless standards not only WiMAX.

In this paper, the transport properties of Hg0.8Cd0.2Te have been investigated at 77K using the hydrodynamic model. We remarked that ionized impurity scattering mechanism plays a dominant role in this material at low electric field. The drift velocity, mean energy and drift mobility are determined as a function of electric field strength. Comparison is made with Monte Carlo and experimental results. The obtained velocity- field curve is in good agreement with reported experimental data.

The temperature effect on pH-ISFET response has been modeled by taking into account the dependence with temperature of the dissociation constants Ka, Kb at the SiO2/Si3N4 electrolyte/insulator interface. The relationship of Ka, Kb versus the temperature is implemented in the development model based in the site-binding model combined with the level 3 of PSPICE model of MOSFET. The model parameters were extracted using genetic algorithm and the simulations results using these values showed a good fit between modeling and experimental data on a large temperature range.

In this work, we analyze the characteristics of the multi-layer ARROW waveguides. The method used is the transfer matrix method. The dependence of the effective index and the attenuation on the waveguide parameters such as number of cladding, contrast of cladding indices, width of the core, and the wavelength has been investigated. The results of our simulation show that the higher the contrast of cladding indices and the lower is the number of cladding necessary to have low loss operation.

Random Telegraph Signal (RTS) noise in submicron MOSFETs showing a capture process, which deviates from the standard Shockley-Read-Hall kinetics, is analyzed using generation-recombination-tunneling model of current modulation in order to explain quadratic dependence of capture rate on current. Proposed model of two-step charge carrier quantum transitions involving secondary trap at the channel and gate oxide interface better represents observed complex switching phenomena in nanoscale devices, as is confirmed by presented experimental results.

In this paper, we present an interactive simulation of a Metal-Oxide-Semiconductor structure, based on a qualitative approach. The code is written in ActionScript / Flash to enjoy all the benefits of this technology in the multimedia field. In addition, our simulation combines theoretical and practical concepts on the same graphical interface: it shows the impact of physical and electrical parameters on the behavior of a MOS structure or a transistor TMOS. Moreover, it provides the physical reasons of the parameters influence that can serve to evaluate the relevance of approximations commonly used. This simulation is applied in engineering education.

Transaction level modeling (TLM) is increasingly being adopted to describe hardware designs at high abstraction levels. This paper proposes a framework that targets the assertion-based verification (ABV) of SystemC transaction level models during simulation. Aspect-oriented (AO) mechanisms are exploited to write temporal properties that fit TLM requirements. No modifications are needed in the design's SystemC code. Functional as well as performance properties are addressed. We demonstrate the effectiveness of our approach on TLM 2.0 standard compliant models.

Global and Environmental variations together are responsible for differences in timing from one die to another for an ASIC design. The tried and tested method of corners and margins is still the dominant method in ASIC industry to assure the timing characteristics of a design. However, the increasing margins limit the scaling of maximum achievable frequency for a given die size, especially because of minimum pulse width violation. The importance of clock tree pulse-width variations due to global N-to-P mismatch is increasing with decreasing pulse width. To continue scaling the clock frequency, we may need to make application specific margins and corners. In this work, we have estimated the impact of pulse width variations on standard cells in a clock library using industrial models and spice simulations. We found that by unbalancing the first stage of a cell with respect to rise and fall edge in a multiple supply voltage design, we could halve the pulse width variations with minimal effect on delay and slew.

Three new Genetic Algorithm approaches are proposed and used to solve a Curve fitting problem for Parasitic Extraction Macro-modeling application. The first approach, Diagonal GA (DGA); is based on replacing the traditional random population initialization method with a deterministic diagonal-like one. The second proposed approach, Elite Condensation GA (ECGA); is based on fine tuning the GA by explicitly condensing the population around a number of elite individuals. The third proposed approach, ECGA2, is a modified version of ECGA; that divides the population into a number of sub-populations where each sub-population is composed of a single elite and a condensed population around it. Then, it performs GA operations on each of those sub-population separately before merging them all into one population and keep repeating that divide-merging sequence. The performances of the three proposed modifications of GA were measured – on an extensive real data sets– and used along with the understanding of the physical problem to offer various explanations of the theoretical aspects of the new algorithms.

Three new Particle Swarm Optimization approaches are proposed. We used these approaches to solve a Curve fitting problem for Parasitic Extraction Macro-modeling application. The first approach is called Wiggling PSO (WPSO); it is an approach where we enforce the particles to vibrate in their motion towards the best position instead of straight motion targeting to larger the scanning area. The second one is called Incrementally Social PSO (ISPSO) which has a variable weight for the social term (xg-xl). This variability enabled us to change the social relationship between the particles from highly repulsive to highly attractive. Finally, we proposed a new Control inspired approach called PID-PSO, where we dealt with PSO motion, as a process needs a controller to be optimized. Many researchers use PSO to tune PID parameters but in this context we used PID to tune PSO motion. Performances were measured on extensive real data sets provided by Mentor Graphics. Based on our understanding of the physical background of the method, various explanations of the theoretical aspects of the new algorithms are presented.

Due to the important increase in equipments and industrial applications, the problems related to the frequency mounting and the effects of interconnections are various (distortion, attenuation, crosstalk,...). Moreover the losses can play a very important role in the degradation and attenuation of signals moving through the line. Taking into consideration the framework of the inter-equipment electromagnetic compatibility (EMC), and skin and proximity effects complicates once again those problems in high frequency, which necessitates, therefore, a physical model adapted to the transmission lines. This paper will expose a behaviour study of the without and with losses multiconductor transmission line –MTL- in frequency domain, based by the modelling of the MTL lines numerical method with the help of Branin model, that can analyze the MTL line by representing in the form of a quadripole, this is an characteristics method, This method would permit the analysis of an MTL line without and with losses and present the advantage of not to presuppose conditions of applied charges to its extremes. This permits it to be introduced easily in circuit simulators as Spice, Esacap and Saber. Diverse examples of applications, by-products of the literature, are presented to validate these method and to show their interests and to comprise the behaviour of a line MTL in the frequency domain.

in this paper a discrete-variable optimization methodology for the automatic design of CMOS integrated spiral inductors is introduced. The use of discrete variable optimization procedure offers the designer the possibility for exploring the design space exclusively in those points available for the technology under use. Further user-defined constraints between layout parameters may also be incorporated as a way of taking into account design heuristics. A comparison between using discrete-variable optimization and a continuous optimization procedure followed by a discretization of the results is presented, where the benefits of the proposed methodology are presented. An application using the proposed methodology was developed in Matlab and the optimization toolbox is used. For the sake of simplicity the Pi-model has been used for characterizing the inductor. The validity of the design results is checked against circuit simulation with ASITIC.

For the past few years modular design has become the de facto standard for the development of complex VLSI systems. Most of these modular VLSI system designs are generally multi objective in nature with the requisite to tradeoff between many contradictory parameters like speed, power consumed, cost and hardware area. They are heavily used in low end ASIC’s which demand low power consumption and cost with acceptable performance and in high end ASIC’s with high performance requirement. This paper presents a novel framework for the optimization of computing architecture based on hierarchy factor method. The determination of this hierarchy factor enables the designer to arrange the various resources of the system in the form of an architecture tree based on the application and the user specifications. The resulting structure would act as a pathway for obtaining the optimal architecture design option for multi objective optimization of the computing architecture used in many VLSI designs. The framework for optimization of computing architecture shown in this paper has been deduced and proved mathematically. The proposed method is capable to determine the most influential resource for a certain performance parameter in the whole system which is deduced by considering the mathematical model of the performance metric. The representation of approach in the form of architecture tree allows easy automation of the process, useful for many multi objective optimized VLSI designs.

Due to technology scaling, modern digital systems are becoming more prone to single-event transients (SETs) caused by radiation strikes in CMOS logic devices. This has led to the need for better soft error detection methods in order to increase the reliability of logic circuits in nanometer technologies. Present day soft error detection techniques assume that soft errors occur due to voltage pulses which change the logic state of a transistor node. A novel soft error detection concept is used, assuming that voltage fluctuations smaller than logic threshold can eventually result in soft errors. Advanced switch-level models were designed which mimic important characteristics of transistor-level circuits like bidirectional signal flow, driving strength variations and node capacitances and use verilog driving strengths to model different voltage values. The resulting switch-level models eliminate the complexity associated with state-of-art transistor level simulators while achieving desired amount of accuracy and faster simulation. The aim of this paper is to interpret various parameters used in these strength-based switch models in order to find an efficient way of injecting transients into complex logic circuits. The approach has been evaluated experimentally by creating a simulation environment which allows transient injection at internal nodes of switch-level circuits and injecting a wide range of input test vectors to ISCAS’85 benchmarks. The simulation results show that transient injection at drains of switch-level circuits gives better results in terms of accuracy and prevents over-estimation of soft error rate calculations as compared to injection at gates of transistors.

In this paper, we present the F4MS (Framework for Mixed Systems) which is a software environment of design, simulation and aided execution of mixed systems. based on components which could be software or/ and hardware, as well as all operational tools allowing to simulate the hardware models. This framework is an extension of the TI4CS framework (Tools Integration For Complex Software),based only on softwares components. To implement mixed systems in this framework we use a general model (execution graph), which characterizes a very important phase (integration) in the design methodology that we propose. This methodology also covers the phases of specification and partitioning. Finally, to illustrate this work we propose an example of mixed system for the implementation of the VPN solutions.

Portable devices are increasingly running complex applications wireless multimedia while at the same time facing stringent implementation constraints. UWB devices are candidates for a wide range of applications. The potential UWB devices will be of short range , portable and capable of delivering high bit rate. Multi-Band Orthogonal Frequency Division Multiplexing (MB-OFDM) being a special case of multicarrier transmission is chosen by WiMedia and EMCA International for its high bit rate capability. To meet this high bit rate requirement while keeping the peak transmitted power under the permitted limit, several bit loading algorithms have been presented in technical literature for OFDM. These algorithms are evaluated and compared on the basis of their theoretical complexity and computation efficiency. However, this theoretical complexity analysis is unable to take into account final implementation issues such as energy consumption and required chip area. In this paper, energy consumption and circuit area estimation of two popular bit-loading algorithms are analyzed in a multiobjective approach and put into evidence the need to analyze new proposals in a more global approach.

Low frequency noise of NMOS and PMOS field effect transistors was measured in wide temperature range as a function of applied electric field intensity in longitudinal and perpendicular direction and the influence of sample geometry on 1/f noise and RTS noise was examined for various gate lengths. Relative amplitude of RTS noise given by number of carriers under the gate and its dependence on channel and gate bias was analyzed.

The constant need for higher speed continues to lead to devices with shorter gate lengths, smaller gate widths, and gate finger spacing. The relationship of between various transistor parameters and the device lifetime is unclear due to the complexity of the problem, and the difficulty and expense of measuring reliability. This paper presents an analytical expression relating the reliability to a transistor’s gate length, based on thermal considerations. Experimental observations support the model’s conclusions.

We present a device structure consisting of a MOS transistor with additional lateral trench gate (LTG). It can be seen as two transistors with surface and lateral gates respectively sharing the same source and drain. The device can be implemented and fabricated in a standard CMOS process with few extra process steps for integrating polysilicon-filled trenches. Current-voltage characterization of the device shows double-threshold-voltage behavior of the lateral-gate transistor, which is due to non-homogenous doping distributions. Due to combined effects of channel-width modulation and shallow-body depletion, the threshold voltage of each transistor can be tuned by the other transistor's gate voltage. Such effects are more pronounced when reducing gate width.

This paper describes a method for reducing the kink effect observed in the I-V output characteristics of a partially depleted SOI MOSFETs. It involves the use of back oxide below drain and source and also below part of the channel. Silvaco TCAD tools are used for fabrication and device simulation. Basic mechanism leading to the generation of kink in SOI MOS devices is studied. Effect of selective back oxide structure with various gap widths and thicknesses help to eliminate the kink effect is also verified. Results obtained through numerical simulations indicated that Kink can be significantly reduced with the use of Selective back oxide structure while preserving the major advantage offered by the conventional SOI structure.

In this paper we carry out study of the Field Plate (FP) effects on the electric characteristics of the HEMTs transistors (high electron mobility transistor) based on AlGaN/GaN heterostructures by modeling the electric field in the structure FP-HEMT (with Field Plate). It consist to analyze the maximum of the electric field according to the gate voltage and drain voltage taking into account several technological parameters of the Field Plate such as the passivation layer thickness, the length of the FP and the distance gate-drain. We have shown that, the FP allows to modify the profile of the distribution of the electric field at the gate edge on the drain side and to reduce the peak of the electric field, thus increasing the breakdown voltage consequently an improvement of the performances of HEMTs.

In this paper, the design of the novel BiCMOS ESD protection circuit with low trigger voltage and fast turn-on speed is proposed. The proposed ESD protection circuit is verified by the transmission line pulse system. The results show that the novel BiCMOS ESD protection circuit has lower trigger voltage of 5.98V compared with that of conventional GGNMOS. And this ESD protection circuit has faster turn-on time of about 37ns than that of the conventional substrate-triggered ESD protection circuit. Also, the ESD protection circuit pass the ESD of HBM 3.2kV and MM 210V.

This paper is analytical study new design for microcantilever based IR sensor. Using hexagonal structure increases energy absorbed, and is useful for the imaging processing after that due to using hexagonal coordinates. Fill factor is also one of the most properties improved in this design. Bimaterial microcantilever is used as a mechanical sensor which is deflected based on the mismatch between the two thermal expansions for the materials used. Maximizing deflection is analyzed and computed NETDTF (Noise Equivalent Temperature Difference) calculated as low as 2.5 mK which proof the good performance of the proposed sensor.

In this paper a modulated light detection smart CMOS image sensor is presented. The design has the ability to sense asynchronous signals transmitted from electronic markers such as flashing light emitting diodes (LEDs) tagged on moving robots. With the presented sensor, object localization and position detection functions are simplified, performed at higher speeds in real time, and power requirement is reduced. The sensor in-pixel processing, filters out the background image data and detects the modulated marker regions. Object localization is facilitated by the use of distributed sensors to cover a more extended space. Since marker locations are extracted locally at each sensor, data transmission rate at each node and power demand is reduced; thus the sensor nodes can be designed as wireless and self powered units. The functionality and power consumption of the proposed design are presented in the 0.35µm standard CMOS technology.

The purpose of this paper is to describe a new method for modulated hysteresis direct torque control algorithm for induction motor (IM) to minimize torque ripple and to obtain a constant switching frequency .The design methodology is based on space vector modulation of electrical machines with digital vector control. MATLAB simulations supported with experimental study under C++ are used. -The simulation and experimental results of this proposed algorithm show adequate dynamic to IM, however the research can be extended to include synchronous motor as well. The implementation of the proposed algorithm in microcontroller embedded systems is described. It requires no PI controller in the torque control loop. Results obtained from simulation and experiments confirmed the feasibility of the proposed strategy comparing to the conventional

Quantum capacitance has an important role in nanoscale device modelling. In the present paper, we investigate the quantum magneto-capacitance of metal-insulator-semiconductor (MIS) structures based on diluted magnetic semiconductors (DMS) in the presence of Rashba spin-orbit interaction (SOI). Typical beating patterns with well defined node-positions in the oscillating quantum capacitance are observed. A simple relation that predicts the positions of nodes in the beating patterns is obtained. The interplay between the giant Zeeman splitting (including s-d exchange interaction) and the Rashba SOI, is discussed.

We have used laser thermal annealing (LTA) to activate shallow B and BF2 implants in p-type Si SOI wafers. Several characterization techniques have been employed in our investigations, such as SiPHER photoluminescence (PL) scans, Sheet resistance measurements (Rs), SIMS and AFM analysis. In sub-melt regime, there is no significant redistribution of implanted dopants; furthermore, BF2 implanted sample exhibits lower boron activation compared with B implanted one. In melt regime, a characteristic box-like doping profile appears, with a depth corresponding to the melting depth controllable by LTA energy setting. However, at a given annealing energy, BF2-implanted Si has a larger melting depth than that the B-implanted one. Besides, a dramatic enhancement in defect curing (PL Increase) and in dopants activation (Rs decrease) has been observed on melting. On the other hand, surface roughness is suddenly increased with the appearance of peaks in surface morphology, around the melting threshold.

In this paper, we present a new method of extracting the model physical parameters of an illuminated solar cell, composed of series and shunt resistance. The method is based on analytical solution of the equation derived from the current-voltage (I-V) characteristics. The equation obtained is expressed in terms of I, V, and the derivative (dI/dV). The model parameters can then be easily determined by numerical fitting. The obtained results show a good agreement with those obtained by the method proposed by Ortiz-Conde et al., and by the five-point method.

In this paper, Maple software is used to study a solar cell modeled by an electronic circuit containing five physical parameters. The physical parameters are: the series resistance, the shunt resistance, the diode reverse saturation current, the diode ideality factor, and the photocurrent (see figure 1). First, the characteristic equation is solved in order to find the output current as a function of the output voltage of the solar cell. Second, the expressions of the short circuit current, the open circuit voltage, the dynamical resistance of the solar cell and different kinds of powers involved: the output power, the power dissipated by Joule Effect in the internal components of the solar cell and the solar cell total power are determined analytically. Finally, the effects of the different physical parameters on the characteristic and on the delivered power of the solar cell are studied and analyzed

GaAs solar cell with graded band gap layer in the back region is analyzed as a function of the electric field created by band gap gradient and the base thickness. Studies are reported at AM 1.5, and unity solar concentration. The optimum thickness of the base region is determined. The performance of the cell strongly depends on the electric field. Comparison with the GaAs cell including high-low junction at the back surface show that the use of back surface field created by graded band gap improve the performance of the GaAs conventional cell.

Arrays of microsensors may be employed for accurate detection of multiple gases possibly existing simultaneously in an environment. They can be made reconfigurable for improving efficiency and reliability. Constituent microsensors in such a reconfigurable array are highly desirable to operate in an ultra low power regime, have a short response time, and take as small chip area as possible. Metal oxide (MOX) materials used for detecting gaseous species usually operate at high temperatures, say, 350 C or beyond. In this work, we introduce and evaluate the use of silica aerogel as the insulating material of choice over the air gap (commonly produced by costly micromachining). Superior properties of aerogel lead to considerable reduction in power consumption and in array chip area while lowering the fabrication cost, based on our extensive simulation evaluation using IntelliSuite software. Silica aerogel is compatible with the CMOS process, ensuring a low overall production cost.

With the expanding market of portable electronic devices such as wireless sensors that would normally exist in great numbers in our surroundings. In some places, access to these sensors is complicated. This makes the handling of changing the batteries difficult, not to mention that these batteries are highly polluting to the environment. This gives the idea to convert the vibration energy, existing in large quantities in our everyday environment into electrical. In this context, the purpose of our study is to design a piezoelectric voltage generator to provide the initial voltage for a system of electrostatic energy harvesting. In our project we will do so early a literature review on piezoelectric transducers, and then designing ELDO / VHDL-AMS model with specified testbench to verify the proposed model and its compatibility with the electrostatic system.

This paper describes an on-chip pumping system and the correspondent driving circuit. The system can be used in lab-on-a-chip applications for pumping the fluids in the microchannels. The device is constituted by two chips placed together: a CMOS chip with the electronics and a glass chip, with the microchannels and the pumping system. This pumping system, wich is the main subject of the article is based on piezoelectric polymer actuators.

This paper presents analytical considerations and practical thoughts leading to the design and implementation of a low power, small-area voltage comparator for pixel-level signal processing in time-based image sensors. The circuit is based on a standard two-stage operational amplifier topology and features an offset suppression technique to minimize the area requirements, a tunable hysteresis and a novel dynamic current control scheme to reduce power consumption. The circuit has been implemented in a QVGA asynchronous pixel array, fabricated in standard 0.18μm CMOS process. We present the circuit concept and design considerations aiming at minimum power consumption and silicon area. Measurements from the fabricated chip are shown and compared to results from theoretical groundwork.

In our modern living era, pressure sensing is one of the most performed measurements to enhance the quality of life. The more advanced technology such as silicon based Micro-electro-mechanical Systems (MEMS) technology is usually explored due to its competitive cost and proven performance. We have explored and implemented the design of MEMS micro pressure sensor on silicon for biomedical applications. Due to the challenging application requirements, many newer designs have been investigated in addition to the previously reported work. Comparisons of the performance of the new designs are herein presented and discussed according to the design stages. A highly proven technology offered by Infineon Technologies SensorNor AS is used in this research and the final implementations are also discussed. The final device is successfully implemented on silicon. In this paper, the extended new unreported design work and the fabrication result are discussed. Future works are also discussed in the final section.