Program for 2015 28th IEEE International System-on-Chip Conference (SOCC)

Time Zhong Hua Banquet Hall Da Xue Tang-2 Da Xue Tang-3 Da Xue Tang-4 Session

Tuesday, September 8

08:30-10:00   T1A: Tutorial: Phase-Locked Clock Generation for SoC: Circuit and System Design Aspects   T1B: Tutorial: SoC Testing  
10:00-10:30 Tea Break
10:30-12:00   T2A: Tutorial: Advanced ESD Protection Design for CMOS Circuits and Systems   T2B: Tutorial: Internet of Things (IoT) - Opportunities for SoC Designers  
12:00-13:30 Lunch Break
13:30-15:00   T3A: Tutorial: From Frequency to Time-Average-Frequency: A paradigm Shift in the Design of Electronic Systems   T3B: Tutorial: A Self-powered Biomedical SoC for Wearable Health Care  
15:00-15:30 Tea Break
15:30-17:00   T4A: Tutorial: Tiny DC-Sourced Single Inductor Charge-Supply ICs   T4B: Tutorial: Emerging Non-volatile Memory: Device, Circuit, and Architecture  

Wednesday, September 9

08:00-08:15 Opening Remarks        
08:15-08:30 Program Overview        
08:30-09:30 Opening Keynote        
09:30-09:45 Tea Break
09:45-10:45 Plenary I        
10:50-12:05 WA1A: Best Paper Nomination I WA1B: RF, Analog & Mixed-Signal I      
12:05-13:30 Lunch Break
13:30-15:10 WP1A: SOC Outreach Workshop Keynotes WP1B: Wireline & Wireless Communications   WP1C: System Level Design Methodologies  
15:10-15:30 Tea Break
15:30-16:45   WP2A: SOC Outreach Workshop Panel   WP2B: Design track  
16:50-18:00 WP: Poster Session with Reception        
19:30-20:40 Legend Of Kung Fu Show at Red Theatre (included in full conference registration, transportation provided)

Thursday, September 10

08:30-09:30 Thursday Keynote        
09:30-10:30 Plenary II        
10:30-10:45 Tea Break
10:45-12:00 TA1: Best Paper Nomination II TA1B: RF, Analog & Mixed-Signal II      
12:00-13:30 Lunch Break
13:30-15:10   TP1A: Embedded Computing Systems & Applications TP1B: High-Level Synthesis & Verification TP1C: NoC & Multicore Architecture  
15:10-15:30 Tea Break
15:30-17:00 Panel Discussion        
19:00-21:30 Banquet Dinner & Keynote (Beijing Fangshan Restaurant - transportation provided)

Friday, September 11

08:30-10:10   FA1A: Memory Systems FA1B: Low Power Systems & Design Methodologies FA1C: Design and CAD Research Opportunities in Post-CMOS Era  
10:10-10:30 Tea Break
10:30-12:10   FA2A: Multi-domain Power Management FA2B: On-Chip Interconnect & 3D-IC FA2C: Emerging VLSI DSP Techniques for Next Generation Communication  
13:30-18:00 Beijing Tour: Tiananmen square, forbidden city, Hutong tour (with rickshaw) - Not included in conference fees

Tuesday, September 8

Tuesday, September 8, 08:30 - 10:00

T1A: Tutorial: Phase-Locked Clock Generation for SoC: Circuit and System Design Aspects

Woogeun Rhee, Tsinghua University, China
Room: Da Xue Tang-2
Chair: Helen Li (University of Pittsburgh, USA)

T1B: Tutorial: SoC Testing

Yu Huang and Janusz Rajski, Mentor Graphics, USA
Room: Da Xue Tang-4
Chair: Yuejian Wu (Infinera, Canada)

Tuesday, September 8, 10:00 - 10:30

Tea Break

Tuesday, September 8, 10:30 - 12:00

T2A: Tutorial: Advanced ESD Protection Design for CMOS Circuits and Systems

Ming-Dou Ker, NCTU, Taiwan
Room: Da Xue Tang-2
Chair: Helen Li (University of Pittsburgh, USA)

T2B: Tutorial: Internet of Things (IoT) - Opportunities for SoC Designers

Ramalingam Sridhar, University Buffalo, USA
Room: Da Xue Tang-4
Chair: Yuejian Wu (Infinera, Canada)

Tuesday, September 8, 12:00 - 13:30

Lunch Break

Tuesday, September 8, 13:30 - 15:00

T3A: Tutorial: From Frequency to Time-Average-Frequency: A paradigm Shift in the Design of Electronic Systems

Liming Xiu, Kairos Microsystems Corp.
Room: Da Xue Tang-2
Chair: Helen Li (University of Pittsburgh, USA)

T3B: Tutorial: A Self-powered Biomedical SoC for Wearable Health Care

Mohammed Ismail, KUSTAR, Abu Dhabi, UAE
Room: Da Xue Tang-4
Chair: Yuejian Wu (Infinera, Canada)

Tuesday, September 8, 15:00 - 15:30

Tea Break

Tuesday, September 8, 15:30 - 17:00

T4A: Tutorial: Tiny DC-Sourced Single Inductor Charge-Supply ICs

Gabriel Rincón-Mora, Georgia Inst. of Tech, USA
Room: Da Xue Tang-2
Chair: Helen Li (University of Pittsburgh, USA)

T4B: Tutorial: Emerging Non-volatile Memory: Device, Circuit, and Architecture

Guangyu Sun, Peking University
Room: Da Xue Tang-4
Chair: Yuejian Wu (Infinera, Canada)

Wednesday, September 9

Wednesday, September 9, 08:00 - 08:15

Opening Remarks

Thomas Buechner, Shao-Jun Wei, Conference General Chairs
Room: Zhong Hua Banquet Hall
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)

Wednesday, September 9, 08:15 - 08:30

Program Overview

Danella Zhao, Program Chair
Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)

Wednesday, September 9, 08:30 - 09:30

Opening Keynote

High-Level Synthesis and Beyond - from Datacenters to IoTs
Jason Cong, Chancellor's Professor, UCLA and Director, Center for Domain-Specific Computing
Room: Zhong Hua Banquet Hall
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)

Wednesday, September 9, 09:30 - 09:45

Tea Break

Wednesday, September 9, 09:45 - 10:45

Plenary I

"Venice: A Cost-effective Architecture for Datacenter Servers"
Rui Hou, VP Processor Design, Suzhou PowerCore
Room: Zhong Hua Banquet Hall
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)

Wednesday, September 9, 10:50 - 12:05

WA1A: Best Paper Nomination I

Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)
WA1A.1 10:50 A 12-bit 1.7mW 20-MS/s DAC with Resistor-String and Current-Steering Hybrid Architecture
Bill Ma and Qinjin Huang (Shenzhen Institute of Advanced Technology, CAS); Fengqi Yu (Shenzhen Institute of Advanced Technology, CAS, P.R. China)
WA1A.2 11:15 A Process-Variation-Aware Multi-Scenario High-Level Synthesis Algorithm for Distributed-Register Architectures
Koki Igawa, Youhua Shi, Masao Yanagisawa and Nozomu Togawa (Waseda University, Japan)
WA1A.3 11:40 Designing a SoC to Control Next-Generation Space Exploration Science Instruments
Xabier Iturbe (California Institute of Technology & ARM, USA); Didier Keymeulen (Jet Propulsion Laboratory/California Institute of Technology, USA); Emre Ozer (ARM, USA); Patrick Yiu (California Institute of Technology, USA); Daniel Berisford (NASA Jet Propulsion Laboratory & California Institute of Technology, USA); Kevin Hand and Robert Carlson (NASA Jet Propulsion Laboratory/ California Institute of Technology, USA)

WA1B: RF, Analog & Mixed-Signal I

Room: Da Xue Tang-2
Chairs: Mohammed Ismail (Khalifa University, United Arab Emirates (UAE)), Peng Liu (Zhejiang University, P.R. China)
WA1B.1 10:50 A 20 GHz High Speed, Low Jitter, High Accuracy and Wide Correction Range Duty Cycle Corrector
Jun Guo, Peng Liu and Weidong Wang (Zhejiang University, P.R. China); Jicheng Chen (State Key Laboratory of High-end Server & Storage Technology, P.R. China); Yingtao Jiang (University of Nevada, Las Vegas, USA)
WA1B.2 11:15 A 5-b 1-GS/s 2.7-mW Binary-Search ADC in 90nm Digital CMOS
Yung-Hui Chung, Cheng-Hsun Tsai and Hsuan-Chin Yeh (National Taiwan University of Science and Technology, Taiwan)
WA1B.3 11:40 All-Digital Deskew Buffer Using a Hybrid Control Scheme
Ting-Li Chu and Wen-Yu Chu (National Yunlin University of Science and Technology, Taiwan); Yasuyoshi Fujii (National Yunlin University of Science and Technology, Japan); Chorng-Sii Hwang (National Yunlin University of Science and Technology, Taiwan)

Wednesday, September 9, 12:05 - 13:30

Lunch Break

Wednesday, September 9, 13:30 - 15:10

WP1A: SOC Outreach Workshop Keynotes

Juergen Becker, Karlsruhe Institute of Technology, Germany; Magdy Bayoumi, University of Louisiana at Lafayette, USA; Michiko Inoue, Nara Institute of Science and Technology, Japan
Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)

WP1B: Wireline & Wireless Communications

Room: Da Xue Tang-2
Chairs: Zhongfeng Wang (Nanjing University, P.R. China), Gabriel Rincón-Mora (Georgia Institute of Technology, USA)
WP1B.1 13:30 A 0.68 pJ/bit Inductor-less Optical Receiver for 20 Gbps with 0.0025mm2 Area in 28 nm CMOS
Laszlo Szilagyi, Ronny Henker and Frank Ellinger (Technische Universität Dresden, Germany)
WP1B.2 13:55 A 320MHz-2.56GHz Low Jitter Phase-Locked Loop with Adaptive-Bandwidth Technique
Seok Min Jung and Janet Roveda (University of Arizona, USA)
WP1B.3 14:20 A 802.15.3c/802.11ad Compliant 24 Gb/s FFT Processor for 60 GHz Communication Systems
Henry Lopez Davila, Chun-Yi Liu, Wei-Chang Liu, Shen-Jui Huang, Shyh-Jye Jou and Sau-Gee Chen (National Chiao Tung University, Taiwan)
WP1B.4 14:45 A 1.2V Wide-Band Reconfigurable Mixer for Wireless Application in 65nm CMOS Technology
Nisha Gupta (Ordnance Factory Campus, Yeddumailaram & Indian Institute of Technology Hyderabad, India); A R Aravinth Kumar (IIT Hyderabad, India); Ashudeb Dutta (Indian Institute of Technology Hyderabad, India); ShivGovind Singh (IIT Hyderabad, India)

WP1C: System Level Design Methodologies

Room: Da Xue Tang-4
Chairs: Yu Wang (Tsinghua University, P.R. China), Suhwan Kim (Seoul National University, Korea)
WP1C.1 13:30 Statistical Rare Event Analysis Using Smart Sampling and Parameter Guidance
Yue Zhao and Hosoon Shin (University of California, Riverside, USA); Haibao Chen (Shanghai Jiao Tong University, P.R. China); Sheldon Tan (University of California, Riverside, USA); Guoyong Shi (Shanghai Jiao Tong University, P.R. China); Xin Li (Carnegie Mellon University, USA)
WP1C.2 13:55 Per-Flow State Management Technique for High-Speed Networks
Xin Yang (Queen's University Belfast, United Kingdom); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom)
WP1C.3 14:20 KnapSim- Run-time Efficient Hardware-Software Partitioning Technique for FPGAs
Kratika Garg, Yan L Aung, Siew Kei Lam and Srikanthan Thambipillai (Nanyang Technological University, Singapore)
WP1C.4 14:45 Optimal Realization of Switched-Capacitor Circuits by Symbolic Analysis
Yanjie Gu and Guoyong Shi (Shanghai Jiao Tong University, P.R. China)

Wednesday, September 9, 15:10 - 15:30

Tea Break

Wednesday, September 9, 15:30 - 16:30

WP2A: SOC Outreach Workshop Panel

Technology, Leadership, Women - Challenges & Opportunities
Michiko Inoue, Nara Institute of Science and Technology, Japan; Yi-Jung Chen, National Chi Nan University, Taiwan; Summer Xinhong Yin, Broadcom Beijing; Junna Zhong, Menter Graphics Shanghai
Room: Da Xue Tang-2
Chair: Ann Gordon-Ross (University of Florida, USA)

Wednesday, September 9, 15:30 - 16:45

WP2B: Design track

Room: Da Xue Tang-4
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)
WP2B.1 15:30 SCREAMER - A Demonstrator Chip for Spectral Noise Optimization by Clock Latency Scheduling
Xin Fan (IHP, Germany); Mikkel B. Stegmann (Teklatech, Denmark); Oliver Schrape (IHP, Germany); Isac Georg Jensen (Teklatech, Denmark); Steffen Zeidler (IHP, Germany); Jannich Thorsen and Tobias Bjerregaard (Teklatech, Denmark); Milos Krstic (IHP, Germany)
WP2B.2 15:45 14nm FinFET Mobile Application Processor with Heterogeneous Multi-Processing Quad-Core CPUs
Hyosig Won, Hyounsoo Park, Wook Kim, Woojin Rim and Jaeyoung Lee (Samsung Electronics, Korea)
WP2B.3 16:00 Scan-Hold-Timing-Friendly Flip-Flop to Improve Chip Routing and Power
Zhe Ge and Miaolin Tan (Freescale Semiconductor, P.R. China)
WP2B.4 16:15 A Robust Architecture for a Complex On-Chip Power Management Controller with External Regulator Handshake for Automotive SOCs
Gautham Shivender Harinarayan and Manmohan Rana (Freescale Semiconductor India (NXP), India); Nishant Singh Thakur (Freescale Semiconductor, India); Akshat Gupta (Freescale Semiconductor India (NXP), India); Himanshu Tiwari (Freescale Semiconductor, India)
WP2B.5 16:30 Low-latency Packet Classification Architectures for an FPGA-based IPv6 Processor
Boris Traskov (Technische Universität Darmstadt, Germany); Dominik Pfeifer and Klaus Hofmann (TU Darmstadt, Germany)

Wednesday, September 9, 16:50 - 18:00

WP: Poster Session with Reception

Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)
WP.1 A Tunable Inverter-Based, Low-Voltage OTA for Continuous-Time ΣΔ ADC
Islam Mostafa (Si-Ware Systems, Cairo, Egypt); Ayman Hassan Ismail (Ain Shams University, Egypt)
WP.2 A High-Gain Low-Power Low-Noise-Figure Differential CMOS LNA with 33% Current-Reused Negative-Conductance Accommodation Structure
To-Po Wang and Shih-Hua Chiang (National Taipei University of Technology, Taiwan)
WP.3 A Comparative Study of multi-GHz LCVCOs Designed in 28nm CMOS Technology
Evan Jorgensen and P. R. Mukund (Rochester Institute of Technology, USA)
WP.4 Multi-Objective Optimization of a Low-Noise Antenna Amplifier for Multi-Constellation Satellite-Navigation Receivers
Josef Dobeš and Jan Michal (Czech Technical University in Prague, Czech Republic); Jakub Popp (CTU, Czech Republic); Martin Grabner (Czech Metrology Institute, Czech Republic); Frantisek Vejrazka and Jakub Kakona (Czech Technical University in Prague, Czech Republic)
WP.5 A Digital-Control Sensorless Current-Mode Boost Converter with Non-Zero Error Bin Compensation and Seamless Mode Transition
Yanqi Zheng, Marco Ho and Ka Nang Leung (The Chinese University of Hong Kong, Hong Kong); Jianping Guo and Biao Chen (Sun Yat-sen University, P.R. China)
WP.6 Novel ECC Structure and Evaluation Method for NAND Flash Memory
Tan Xue-qing, Jiang Xiao-bo and Huang Wei-pei (South China University of Technology, P.R. China)
WP.7 Floorplan and Congestion Aware Framework for Optimal SRAM Selection for Memory Subsystems
Gaurav Narang (IIIT DELHI & STMicroelectronics, India); Prakhar Raj Gupta (Indian Institute of Technology, Delhi & ST Microelectronics India, India); Alexander Fell (IIIT Delhi, India); Anuj Grover (ST Microelectronics, India)
WP.8 An Improved Distributed Video Coding with Low-Complexity Motion Estimation At Encoder
Hsin-Ping Yang and Hsiao-Chi Hsieh (National Taiwan University, Taiwan); Sheng-Hsiang Chang (National Taiwan University, USA); Sao-Jie Chen (National Taiwan University, Taiwan)
WP.9 Modelling Visual Attention Towards Embodiment Cognition on a Reconfigurable and Programmable System
Shufan Yang (University of Wolverhampton & Hunan University, United Kingdom); Renfa Li and Qiang Wu (Hunan University, P.R. China)
WP.10 A Filter Design to Increase Accuracy of Lucy- Richardson Deconvolution for Analyzing RTN Mixtures Effects on VLSI Reliability Margin
Hiroyuki Yamauchi (Fukuoka Institute of Technology, Japan); Worawit Somha (KMITL, Thailand); Yuan-Qiang Song (Fukuoka Institute of Technology, Japan)
WP.11 Analysis of a Serial Link for Power Supply Induced Jitter
Jai Narayan Tripathi (STMicroelectronics Pvt. Ltd. & INDIA, India); Hiten Advani and Raj Kumar Nagpal (Synopsys, India); Vijender Sharma (Indraprastha Institute of Information Technology, India); Rakesh Malik (ST Microelectronics, India)
WP.12 Formal Equivalence Checking Between SLM and RTL Descriptions
Jian Hu (National University of Defense Technology, School of Computer, P.R. China); Tun Li and Sikun Li (National University of Defence Technology, P.R. China)
WP.13 An Accelerator for Classification Using Radial Basis Function Neural Network
Mahnaz Mohammadi, Rohit Ronge, Jayesh Ramesh Chandiramani and Soumitra Nandy (Indian Institute of Science, India)
WP.14 Reconfigurable Hardware Architecture of the Spatial Pooler for Hierarchical Temporal Memory
Dhireesha Kudithipudi (Rochester Institute of Technology, USA); Abdullah M. Zyarah (University of Baghdad, Iraq)
WP.15 Low-Voltage 9T FinFET SRAM Cell for Low-Power Applications
Farshad Moradi (Aarhus University & Integrated Circuits and Electronics Lab., Denmark)
WP.16 Low Power Design for On-chip Networking Processing System
Jie Jin (The Rince Institute, Dublin City University, Dublin 9, Ireland); Feng Guo (The Rince Institute, Dublin City University, Ireland); Xiaojun Wang (Dublin City University, Ireland); Lingling Sun (Hangzhou Dianzi University, P.R. China)
WP.17 A High Throughput Router with a Novel Switch Allocator for Network on Chip
Pengzhan Yan, Shixiong Jiang and Ramalingam Sridhar (University at Buffalo, USA)
WP.18 Fault-Resilient Routing Unit in NoCs
Xiaofan Zhang (University of Electronic Science and Technology of China (UESTC), P.R. China); Masoumeh Ebrahimi (University of Turku & KTH Royal Institute of Techology, Finland); Huang Letian (University of Electronic Science and Technology of China, P.R. China); Guang-Jun Li (UESTC, P.R. China)
WP.19 A 9-bit, 110-MS/s Pipelined-SAR ADC Using Time-Interleaved Technique with Shared Comparator
Taehoon Kim (Seoul National University, Korea); Sunkwon Kim (Samsung Electronics, Korea); Jong-Kwan Woo (University of Michigan, Korea); Hyongmin Lee and Suhwan Kim (Seoul National University, Korea)
WP.20 Design of A 12-bit 0.83 MS/s SAR ADC for an IPMI SoC
Han Zhou, Xiaoyan Gui and Peng Gao (Beijing Institute of Technology, P.R. China)
WP.21 Instruction Decoders Based on Pattern Factorization
Ricardo Santos (Federal University of Mato Grosso do Sul, Brazil); Renan Marks, Rafael Alves and Felipe Oliveira (UFMS, Brazil); Renato Santos (IFMS, Brazil)
WP.22 A Multi-level Collaboration Low-power Design Based on Embedded System
Xiang Wang and LI Lin (Beihang University, P.R. China); Zhang Longbin (Institute of Computing Technology Chinese Academy of Sciences, P.R. China); Weike Wang, Rong Zhang, Yi Zhang and Shen Quanneng (Beihang University, P.R. China)
WP.23 A Deterministic, Minimal Routing Algorithm for a Toroidal, Rectangular Honeycomb Topology Using a 2-tupled Relative Address
Alexander Fell (IIIT Delhi, India); Nandy S (Indian Institute of Science, India); Ranjani Narayan (Morphing Machines, India)
WP.24 An A-SAR ADC Circuit with Adaptive Auxiliary Comparison Scheme
Haibo Wang (Southern Illinois University Carbondale, USA); Suresh Koyada, Abhilash Karnatakam Nagabhushana and Stefan Leitner (Southern Illinois University, USA)
WP.25 VCAS: Viewing Context Aware Power-Efficient Mobile Video Embedded Memory
Dongliang Chen, Xin Wang and Jinhui Wang (North Dakota State University, USA); Na Gong (NDSU, USA)

Wednesday, September 9, 19:30 - 20:40

Legend Of Kung Fu Show at Red Theatre (included in full conference registration, transportation provided)

Thursday, September 10

Thursday, September 10, 08:30 - 09:30

Thursday Keynote

Five Forces Shaping the Silicon World: Advanced sensing and intelligence in IoT and vision
Chris Rowen, Fellow and CTO IP Group Cadence Design Systems, Inc.
Room: Zhong Hua Banquet Hall
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)

Thursday, September 10, 09:30 - 10:30

Plenary II

Unicorns and Centaurs: Architecting SOCs for Software Defined Networking
Gavin Stark, Chief Scientist, Netronome
Room: Zhong Hua Banquet Hall
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)

Thursday, September 10, 10:30 - 10:45

Tea Break

Thursday, September 10, 10:45 - 12:00

TA1: Best Paper Nomination II

Room: Zhong Hua Banquet Hall
Chair: Danella Zhao (University of Louisiana at Lafayette, USA)
TA1.1 10:45 Can Systems Extend to Polymer? SoP Architecture Design and Challenges
Ujjwal Gupta, Sankalp Jain and Umit Ogras (Arizona State University, USA)
TA1.2 11:10 FAcET: Fast and Accurate Power/Energy Estimation Tool for CPU-GPU Platforms At Architectural-Level
Santhosh Rethinagiri (BSC-Microsoft Research Centre & Barcelona Supercomputing Center, Spain); Oscar Palomar, Francisco Javier Arias Moreno, Osman Unsal and Adrian Cristal (Barcelona Supercomputing Center, Spain)
TA1.3 11:35 Symmetric Write Operation for 1T-1MTJ STT-RAM Cells Using Negative Bitline Technique
Hooman Farkhani (Ferdowsi University of Mashhad, Denmark); Ali Peiravi (Ferdowsi University of Mashhad, Iran); Jens Madsen (Aarhus University, Denmark); Farshad Moradi (Aarhus University & Integrated Circuits and Electronics Lab., Denmark)

TA1B: RF, Analog & Mixed-Signal II

Room: Da Xue Tang-2
Chairs: Guoyong Shi (Shanghai Jiao Tong University, P.R. China), Andrew Marshall (University of Texas at Dallas, USA)
TA1B.1 10:45 A PAM-4 Adaptive Analog Equalizer with Decoupling Control Loops for 25-Gb/s CMOS Serial-Link Receiver
Shunbin Li, Peng Liu and Weidong Wang (Zhejiang University, P.R. China); Xing Fang, Dong Wu and Xianghui Xie (State Key Laboratory of Mathematical Engineering and Advanced Computing, P.R. China)
TA1B.2 11:10 Low Noise Output Stage for Oversampling Audio DAC
Yujin Park, Han Yang and Hyunjong Kim (Seoul National University, Korea); Jun Soo Cho (Seoul National University & Inter-university Semiconductor Research Center, Korea); Suhwan Kim (Seoul National University, Korea)
TA1B.3 11:35 A Digital Background Calibration Technique for Split DAC Based SAR ADC by Using Redundant Cycle
Wuguang Wang (Zhejiang University, P.R. China); Rulin Huang (Zhejiang University & Institute of VLSI Design, P.R. China); Guoquan Sun (ZheJiang University, P.R. China); Weijun Mao and Xiaolei Zhu (Zhejiang University, P.R. China)

Thursday, September 10, 12:00 - 13:30

Lunch Break

Thursday, September 10, 13:30 - 15:10

TP1A: Embedded Computing Systems & Applications

Room: Da Xue Tang-2
Chairs: Sao-Jie Chen (National Taiwan University, Taiwan), Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom)
TP1A.1 13:30 A 61 μA/MHz Reconfigurable Application-Specific Processor and System-on-Chip for Internet-of-Things
Yuxiang Huan (Fudan University, P.R. China); Ning Ma (Royal Institute of Technology (KTH), Sweden); Stefan Blixt (Imsys Technologies AB, Sweden); Zhuo Zou (KTH-The Royal Institute of Technology, Sweden); Lirong Zheng (Fudan University, P.R. China)
TP1A.2 13:55 A Point of Care Electrochemical Impedance Spectroscopy Device
Zhijian Lu (Arizona state University, USA); Hongyi Wang (Xi'an Jiaotong University, P.R. China); Syed Naqvi (Intel, USA); Yuji Zhao (Arizona state University, USA); Hongjiang Song (Intel, USA); Jennifer M Blain Christen (Arizona State University, USA)
TP1A.3 14:20 Energy-Efficient Gas Recognition System with Event-Driven Power Control
Chun-Ying Huang (National Chiao-Tung University, USA); Po-Tsang Huang and Chih-Chao Yang (National Chiao-Tung University, Taiwan); Ching-Te Chuang and Wei Hwang (National Chiao Tung University, Taiwan)
TP1A.4 14:45 Loop Acceleration and Instruction Repeat Support for Application Specific Instruction-set Processors
Zhenzhi Wu (Beijing Institute of Technology); Dake Liu and Xiaoyang Li (Beijing Institute of Technology, P.R. China)

TP1B: High-Level Synthesis & Verification

Room: Da Xue Tang-3
Chairs: Yu Huang (Mentor Graphics, USA), Michiko Inoue (Nara Institute of Science and Technology, USA)
TP1B.1 13:30 Synthesis and Verification of Cyclic Combinational Circuits
Jui-Hung Chen (National Tsing Hua University, Taiwan); Yung-Chih Chen (Yuan Ze University, Taiwan); Wan-Chen Weng, Ching-Yi Huang and Chun-Yao Wang (National Tsing Hua University, Taiwan)
TP1B.2 13:55 Partitioning-Based Multiplexer Network Synthesis for Field-Data Extractors
Koki Ito (Waseda University, Japan); Yutaka Tamiya (Fujitsu Laboratories Ltd., Japan); Masao Yanagisawa and Nozomu Togawa (Waseda University, Japan)
TP1B.3 14:20 A Scan Segmentation Architecture for Power Controllability and Reduction
Zhou Jiang, Dong Xiang and Kele Shen (Tsinghua University, P.R. China)
TP1B.4 14:45 Optimization of Best Polarity Searching for Mixed Polarity Reed-Muller Logic Circuit
Limin Xiao, Zhenxue He, Li Ruan, Rong Zhang, Tongsheng Xia and Xiang Wang (Beihang University, P.R. China)

TP1C: NoC & Multicore Architecture

Room: Da Xue Tang-4
Chairs: Ann Gordon-Ross (University of Florida, USA), Yinhe Han (Institute of Computing Technology, Chinese Academy of Sciences, P.R. China)
TP1C.1 13:30 A Novel Flow Fluidity Meter for BiNoC Bandwidth Resource Allocation
Wen-Chung Tsai (Chaoyang University of Technology); Hsiao-En Lin (Marvell Taiwan Ltd., Taiwan); Ying-Cherng Lan (National Taiwan University); Sao-Jie Chen (National Taiwan University, Taiwan); Yu Hen Hu (University of Wisconsin-Madison, USA)
TP1C.2 13:55 Low-Latency Power-Efficient Adaptive Router Design for Network-on-Chip
Nasim Nasirian (University of Louisiana at Lafayette, USA); Magdy Bayoumi (University of Louisiana, USA)
TP1C.3 14:20 A Novel Fault-Tolerant Router Architecture for Network-on-Chip Reconfiguration
Pengzhan Yan, Shixiong Jiang and Ramalingam Sridhar (University at Buffalo, USA)
TP1C.4 14:45 Adaptive CDMA Based Multicast Method for Photonic Networks on Chip
Soumyajit Poddar (Indian Institute of Engineering Science and Technology, Shibpur, India); Prasun Ghosal (Indian Institute of Engineering Science and Technology, Shibpur & University of North Texas, India); Hafizur Rahaman (Indian Institute of Engineering Science and Technology, Shibpur)

Thursday, September 10, 15:10 - 15:30

Tea Break

Thursday, September 10, 15:30 - 17:00

Panel Discussion

How to Avoid Internet of "Broken" Things - Challenges in Integration, Reliability, Security and Scalability
Shin-Ming Liu, Chief Scientist, Intel Labs China; Gavin Stark, Chief Scientist, Netronome; Yervant Zorian, Chief Architect and Fellow, Synopsys; Lan Chen, Professor & Deputy Director of China R&D Center for Internet of Things, CAS; Zhong Chen, Professor of EECS, Peking University; YongPan Liu, Associate Professor of EE, Tsinghua University
Room: Zhong Hua Banquet Hall
Chair: Magdy Bayoumi (University of Louisiana, USA)

Thursday, September 10, 19:00 - 21:30

Banquet Dinner & Keynote (Beijing Fangshan Restaurant - transportation provided)

Yervant Zorian, Chief Architect and Fellow, Synopsys
Chair: Thomas Buechner (IBM Germany Research & Development, Germany)

Friday, September 11

Friday, September 11, 08:30 - 10:10

FA1A: Memory Systems

Room: Da Xue Tang-2
Chairs: Juergen Becker (Karlsruhe Institute of Technology, Germany), Guangyu Sun (Peking University, P.R. China)
FA1A.1 08:30 A 128-kb 10% Power Reduced 1T High Density ROM with 0.56ns Access Time Using Bitline Edge Sensing in Sub 16 nm Bulk FinFET Technology
Vaibhav Verma, Sachin Taneja, Pritender Singh and Sanjeev Kumar Jain (Synopsys India Private Limited, India)
FA1A.2 08:55 A 6T SRAM Cell Based Pipelined 2R/1W Memory Design Using 28nm UTBB-FDSOI
Ramandeep Kaur (IIIT-Delhi, India); Harsh Rawat (STMicroelectronics, India); Alexander Fell (IIIT Delhi, India)
FA1A.3 09:20 Statistical Analysis and Parametric Yield Estimation of Standard 6T SRAM Cell for Different Capacities
Anil Gundu Kumar (IIIT Delhi, India); Mohammad Hashmi (IIITD, India); Ramkesh Sharma (ST Microelectronics, India); Naushad Ansari (IIIT Delhi, India)
FA1A.4 09:45 Memory Cost Analysis for OpenFlow Multiple Table Lookup
Keissy Guerra Perez (Queen University of Belfast, United Kingdom); Sandra Scott-Hayward and Xin Yang (Queen's University Belfast, United Kingdom); Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom)

FA1B: Low Power Systems & Design Methodologies

Room: Da Xue Tang-3
Chairs: Shiyan Hu (Michigan Technological University, USA), Yuejian Wu (Infinera, Canada)
FA1B.1 08:30 A -30 Dbm Sensitive Ultra Low Power RF Energy Harvesting Front End with an Efficiency of 70.1% At -22 Dbm
Nagaveni Vamsi, Pramod Kaddi and Ashudeb Dutta (Indian Institute of Technology Hyderabad, India); ShivGovind Singh (IIT Hyderabad, India)
FA1B.2 08:55 Evaluation of Energy-Efficient Latch Circuits with Hybrid Tunneling FET and FinFET Devices for Ultra-Low-Voltage Applications
Tse-Ching Wu, Chien-Ju Chen, Yin-Nien Chen, Vita Hu, Pin Su and Ching-Te Chuang (National Chiao Tung University, Taiwan)
FA1B.3 09:20 A High Speed and Low Power Content-addressable Memory(CAM) Using Pipelined Scheme
Shixiong Jiang, Pengzhan Yan and Ramalingam Sridhar (University at Buffalo, USA)

Friday, September 11, 08:30 - 09:45

FA1C: Design and CAD Research Opportunities in Post-CMOS Era

Special Session I
Room: Da Xue Tang-4
Chairs: Yiyu Shi (Missouri Univ of Science & Technology, USA), Guojie Luo (Peking University, P.R. China)
08:30 The Evolutionary Spintronic Technologies and Their Usage in High Performance Computing
Helen Li and Xiuyuan Bi (University of Pittsburgh, USA); Zhenyu Sun (Broadcom, USA)
08:55 On Microarchitectural Modeling for CNFET-based Circuits
Tianjian Li, Hao Chen, Weikang Qian, Xiaoyao Liang and Li Jiang (Shanghai Jiao Tong University, P.R. China)
09:20 Timing-Driven Placement for Carbon Nanotube Circuits
Wang Chen (Shanghai Jiao Tong University); Li Jiang (Shanghai Jiao Tong University, P.R. China); Shiyan Hu (Michigan Technological University, USA); Tianjian Li, Xiaoyao Liang, Naifeng Jing and Weikang Qian (Shanghai Jiao Tong University, P.R. China)

Friday, September 11, 10:10 - 10:30

Tea Break

Friday, September 11, 10:30 - 12:10

FA2A: Multi-domain Power Management

Room: Da Xue Tang-2
Chairs: Mohammed Ismail (Khalifa University, United Arab Emirates (UAE)), Ramalingam Sridhar (University at Buffalo, USA)
FA2A.1 10:30 Cascoded Flipped Voltage Follower Based Output-Capacitorless Low-Dropout Regulator for SoCs
Guangxiang Li and Jianping Guo (Sun Yat-sen University, P.R. China); Yanqi Zheng (Sun Yat-sen University); Mo Huang (University of Macau, P.R. China); DiHu Chen (Sun Yat-Sen University, P.R. China)
FA2A.2 10:55 A Fully Integrated Charge Sharing Active Decap Scheme for Power Supply Noise Suppression
Ahmed M Ammar and Rafik Guindi (Nile University, Egypt); Ethan Shih, Carlos Tokunaga, Jim Tschanz and Muhammad Khellah (Intel Corporation, USA)
FA2A.3 11:20 ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Pins of Battery-Monitoring IC
Chia-Tsen Dai and Ming-Dou Ker (National Chiao-Tung University, Taiwan)
FA2A.4 11:45 High-PSR CMOS LDO with Embedded Ripple Feed-Forward and Energy-Efficient Bandwidth Extension
Liuyan Chen (Sun Yat-sen University & SYSU-CMU Shunde International Joint Research Institute, P.R. China); Qi Cheng, Jianping Guo and Min Chen (Sun Yat-sen University, P.R. China)

FA2B: On-Chip Interconnect & 3D-IC

Room: Da Xue Tang-3
Chairs: Sao-Jie Chen (National Taiwan University, Taiwan), Sakir Sezer (Queen's University Belfast & CTO Titan IC, United Kingdom)
FA2B.1 10:30 Exploiting Multi-Band Transmission Line Interconnects to Improve the Efficiency of Cache Coherence in Multiprocessor System-on-Chip
Qi Hu, Kejun Wu and Peng Liu (Zhejiang University, P.R. China)
FA2B.2 10:55 Research on Crosstalk Issue of Through Silicon Via for 3D Integration
Ting Kang and Zhaowen Yan (Beihang University, P.R. China); Wei Zhang and Jianwei Wang (Beihang University of China, P.R. China)
FA2B.3 11:20 Analysis and Design of High Performance Wireless Power Delivery Using On-chip Octagonal Inductor in 65-nm CMOS
Weijun Mao, Liusheng Sun, Junwei Xu, Jiajia Wu and Xiaolei Zhu (Zhejiang University, P.R. China)
FA2B.4 11:45 A Novel Thermal-Aware Structure of TSV Cluster
Jingyan Fu and Ligang Hou (Beijing University of Technology, P.R. China); Jinhui Wang (North Dakota State University, USA); Bo Lu (Beijing University of Technology); Wei Zhao and Yang Yang (Beijing University of Technology, P.R. China)

FA2C: Emerging VLSI DSP Techniques for Next Generation Communication

Special Session II
Room: Da Xue Tang-4
Chairs: Chuan Zhang (National Mobile Communications Research Laboratory, Southeast University, P.R. China), Liping Li (Anhui University, P.R. China)
10:30 High-throughput MQ Encoder for Pass-Parallel EBCOT in JPEG2000
Na Bao and Zhiheng Qi (Tianjin University, P.R. China); Zhe Jiang (Peking University, P.R. China); Wei Zhang (Tianjin University, P.R. China)
10:55 On the Encoding Complexity of Systematic Polar Codes
Liping Li (Anhui University, P.R. China); Wenyi Zhang (University of Science and Technology of China, P.R. China)
11:20 Efficient Stochastic List Successive Cancellation Decoder for Polar Codes
Xiao Liang, Chuan Zhang and Menghui Xu (National Mobile Communications Research Laboratory, Southeast University, P.R. China); Shunqing Zhang (ICRI-MNC, Intel Labs, P.R. China); Xiaohu You (National Mobile communication Research Lab., Southeast University, P.R. China)
11:45 EM Independent Gaussian Approximate Message Passing and Its Application in OFDM Impulsive Noise Mitigation
Yun Chen, Yuanzhou Hu, Yizhi Wang and Xiaoyang Zeng (Fudan University, P.R. China); Defeng Huang (University of Western Australia, Australia)

Friday, September 11, 13:30 - 18:00

Beijing Tour: Tiananmen square, forbidden city, Hutong tour (with rickshaw) - Not included in conference fees

Friday, September 11, 13:30 - 14:30

Tech tour of Spreadtrum Communications, Inc.

Welcome & Introduction
Yi Kang, VP of Spreadtrum